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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M16C/29 датащи(PDF) 195 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 195 Page - Renesas Technology Corp |
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195 / 499 page  14. Serial I/O p u o r G 9 2 / C 6 1 M page 171 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 14.1 Block diagram of UARTi (i = 0 to 2) Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock source selection Internal External CTS/RTS disabled CTS/RTS selected RxD0 1 / (n0+1) 1/16 1/16 1/2 U0BRG register CLK0 CTS0 / RTS0 f1SIO or f2SIO f8SIO f32SIO VCC RTS0 CTS0 TxD0 (UART0) CLK1 to CLK0 002 012 102 CKDIR=0 CKDIR=1 CKPOL CKDIR=0 CKDIR=1 CRS=1 CRS=0 CRD=0 CRD=1 RCSP=0 RCSP=1 VCC CRD=0 CRD=1 UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Receive clock Transmit clock Reception control circuit Transmission control circuit Transmit/ receive unit CLK polarity reversing circuit CTS/RTS disabled CTS0 from UART1 UART reception Clock synchronous type RxD1 TxD1 (UART1) 1 / (n1+1) 1/16 1/16 1/2 U1BRG register CLK1 f1SIO or f2SIO f8SIO f32SIO CLK1 to CLK0 002 012 102 CKDIR=0 CKDIR=1 CKPOL CKDIR=0 CKDIR=1 VCC CRD=0 CRD=1 CLKMD0=0 CLKMD1=0 CRS=1 CRS=0 RCSP=0 RCSP=1 CLKMD0=1 CLKMD1=1 Clock source selection Internal External UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Receive clock Transmit clock Reception control circuit Transmission control circuit Transmit/ receive unit Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected) CLK polarity reversing circuit RTS1 CTS1 Clock output pin select CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CTS0 from UART0 CTS1 / RTS1/ CTS0/ CLKS1 i = 0 to 2 ni: Values set to the UiBRG register SMD2 to SMD0, CKDIR: Bists in the UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register CLKMD0, CLKMD1, RCSP: Bits in the UCON register RxD2 CLK2 CTS2 / RTS2 RTS2 CTS2 TxD2 (UART2) 1 / (n2+1) 1/16 1/16 1/2 U2BRG register f1SIO or f2SIO f8SIO f32SIO CLK1 to CLK0 002 012 102 CKDIR=0 CKDIR=1 CKPOL CKDIR=0 CKDIR=1 CRS=1 CRS=0 VCC CRD=0 CRD=1 Reception control circuit Transmission control circuit UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Receive clock Transmit clock RxD polarity reversing circuit Internal External Clock source selection TxD polarity reversing circuit Transmit/ receive unit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected Main clock, PLL clock, or on-chip oscillator clock 1/2 1/8 1/4 f1SIO f2SIO f8SIO f32SIO f1SIO or f2SIO PCLK1=1 PCLK1=0 |
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