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M16C/29 датащи(PDF) 156 Page - Renesas Technology Corp

номер детали M16C/29
подробное описание детали  RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
PDF  499 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M16C/29 датащи(HTML) 156 Page - Renesas Technology Corp

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12. Timer (Three-phase Motor Control Timer Function)
p
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r
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9
2
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6
1
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page 132
8
5
4
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o
7
0
0
2
,
0
3
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a
M
2
1
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2
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Figure 12.31 TB2 Register, TRGSR Register, and TABSR Register
Symbol
Address
After Reset
TB2
039516-039416
Undefined
b7
b0 b7
b0
(b15)
(b8)
RW
000016 to FFFF16
Function
Setting Range
Timer B2 Register (1)
NOTE:
1. Access the register by 16 bit units.
RW
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
TA1TGL
Symbol
Address
After Reset
TRGSR
038316
0016
Timer A1 event/trigger
select bit
To use the V-phase output control
circuit, set these bits to “01 2”(TB2
underflow).
Trigger Select Register
Bit Name
Function
Bit Symbol
b0
To use the W-phase output control
circuit, set these bits to “01 2”(TB2
underflow).
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA2 is selected (2)
1 1 : TA4 is selected (2)
To use the U-phase output control
circuit, set these bits to “01 2”(TB2
underflow).
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
RW
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b5 b4
NOTES:
1. Set the corresponding port direction bit to 0 (input mode).
2. Overflow or underflow.
b7 b6 b5 b4 b3 b2 b1
Symbol
Address
After reset
TABSR
038016
0016
Count Start Flag
Bit Name
Function
Bit Symbol
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag
0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW



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