M306V2EEFS datasheet(176/271 Pages) RENESAS

176 / 271 page

Rev.1.40

Oct 06, 2004 page 176 of 269

M306V2ME-XXXFP, M306V2EEFP

Figure 2.15.1 HSYNC counter register

2.15 HSYNC Counter

The synchronous signal counter counts HSYNC from HSYNC count input pins (HC0/P75, HC1/P77) as a

count source.

The count value in a certain time (T time; 1024 µs, 2048 µs, 4096 µs and 8192 µs) divided system clock f32

is stored into the 8-bit latch.

Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “FF16,” “FF16”

is stored into the latch.

The latch value can be obtained by reading out the HSYNC counter latch (address 027F16). A count source

and count update cycle (T time) are selected by bits 0, 3 and 4 of the HSYNC counter register.

Figure 2.15.1 shows the HSYNC counter and Figure 2.15.2 shows the synchronous signal counter block

diagram.

Note: When using the HSYNC counter, set bit 7 of the peripheral mode register (address 027D16) according

to the main clock frequency.

Figure 2.15.2 HSYNC counter block diagram

b7 b6 b5 b4 b3 b2 b1 b0

HSYNC counter register

Count source switch bit

Input polarity

switch bit

Function

Bit name

Nothing is assigned. In an attempt to write to this bit, write “0.”

The value, if read, turns out to be “0.”

Count freguency

selection bits

b4 b3 <Count freguency>

0 0 : 1024 µs

0 1 : 2048 µs

1 0 : 4096 µs

1 1 : 8192 µs

0 :

1 :

(Falling edge count)

(Rising edge count)

Note: When HC0 and HC1 input are positive polarity (negetive polarity),

HIGH width (LOW width) needs 3 main clock cycles or more of system clock.

0 : HC0/P75 pin input

1 : HC1/P77 pin input

Bit symbol

HCC0

HCC1

HCC3

Symbol

Address

When reset

027E16

XXX00X0016

HCC4

Nothing is assigned. In an attempt to write to these bits, write “0.”

The value, if read, turns out to be “0.”

Reset

8-bit counter

Latch (8 bits)

HC0/P75

HC1/P77

Counter

HSYNC

counter latch

Data bus

Selection gate : connected to black

side when reset.

System clock f32

HCC0

Polarity switch

1024

µs

2048

µs

4096

µs

8192

µs

HCC3, HCC4

HCC1

Freguency divider

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