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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 125 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 125 Page - Renesas Technology Corp |
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125 / 271 page  Rev.1.40 Oct 06, 2004 page 125 of 269 M306V2ME-XXXFP, M306V2EEFP Item Specification Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3) • Framing error (see the specifications of clock-asynchronous serial I/O) • Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TxD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a transmission interrupt occurs • The error sum flag (see the specifications of clock-asynchronous serial I/O) Table 2.11.9 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) (2) Notes 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. 2: fEXT is input from the CLK2 pin. 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. |
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