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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 122 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 122 Page - Renesas Technology Corp |
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122 / 271 page  Rev.1.40 Oct 06, 2004 page 122 of 269 M306V2ME-XXXFP, M306V2EEFP (2) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 2.11.24 shows the ex- ample of timing for switching serial data logic. Figure 2.11.24 Timing for switching serial data logic ST : Start bit P : Even parity SP : Stop bit D0 D1 D2 D3 D4 D5 D6 D7 P SP ST SP ST D3 D4 D5 D6 D7 P D0 D1 D2 Transfer clock TxD2 (no reverse) TxD2 (reverse) “H” “L” “H” “L” “H” “L” • When LSB first, parity enabled, one stop bit (3) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (1) Sleep mode (UART0) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UART0. The sleep mode is selected when the sleep select bit (bit 7 at address 03A016) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. |
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