M306V2EEFS datasheet(121/271 Pages) RENESAS

121 / 271 page

Rev.1.40

Oct 06, 2004 page 121 of 269

M306V2ME-XXXFP, M306V2EEFP

<UART2, UART0>

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 2.11.23 Typical transmit/receive timings in UART mode

<UART2>

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

D0 D1 D2 D3

D4 D5 D6

Start

bit

Parity

bit

Cleared to “0” when interrupt request is accepted, or cleared by software

D0 D1 D2 D3 D4 D5 D6 D7

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit register

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

Transmit register

empty flag (TXEPT)

“0”

“1”

“0”

“1”

“0”

“1”

Transmit interrupt

request bit (IR)

“0”

“1”

Transfer clock

TxD2

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “1”.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f 1, f8, f32)

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

Start bit

Sampled “L”

Receive data taken in

BRGi count

source

Receive enable bit

RxDi

Transfer clock

Receive

complete flag

RTSi

Stop bit

“1”

“0”

“1”

“H”

“L”

The above timing applies to the following settings :

•Parity is disabled.

bit

Receive interrupt

request bit

“0”

“1”

Cleared to “0” when interrupt request is accepted, or cleared by software

Transfered from UARTi receive register to

UARTi receive buffer register

Reception triggered when transfer clock

is generated by falling edge of start bit

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