OR4 datasheet(27/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Embedded Block RAM (EBR) (continued)

FIFO Modes

FIFOs can be conﬁgured to 256, 512, or 1K depths and

36, 18, or 9 widths respectively but also can be

expanded using multiple blocks. FIFO works synchro-

nously with the same read and write clock where the

read port can be registered on the output or not regis-

tered. It can also be optionally conﬁgured asynchro-

nously with different read and write clocks and the

same read port register options.

Integrated ﬂags allow the user the ability to fully utilize

the EBR for FIFO, without the need to dedicate an

address for providing distinct full/empty status. There

are four programmable ﬂags provided for each FIFO:

Empty, partially empty, full, and partially full FIFO sta-

tus. The partially empty and partially full ﬂags are pro-

grammable with the ﬂexibility to program the ﬂags to

any value from the full or empty threshold. The pro-

grammed values can be set to a ﬁxed value through the

bitstream or a dynamic value can be controlled by input

pins of the EBR FIFO. When the FIFO is in asynchro-

nous mode, the FIFO ﬂags use grey code counters to

ensure proper glitch-free operation.

Multiplier Modes

The ORCA Series 4 EBR supports two variations of

multiplier functions. Constant coefﬁcient MULTIPLY

[KCM] mode will produce a 24-bit output of a ﬁxed 8-bit

constant multiply of a 16-bit number or a ﬁxed 16-bit

constant multiply of an 8-bit number. This KCM multi-

plies a constant times a 16- or 8-bit number and pro-

duces a product as a 24-bit result. The coefﬁcient and

multiplication tables are stored in memory. The input

can be conﬁgured to be registered for pipelining. Both

write ports are available during MULTIPLY mode so

that the user logic can update and modify the coefﬁ-

cients for dynamic coefﬁcient updates. The SCUBA

program in ispLEVER should be used to create the

KCM multipliers, including the input of initial coefﬁ-

cients.

An 8 x 8 MULTIPLY mode is conﬁgurable to either a

pipelined or combinatorial multiplier function of two 8-

bit numbers. Two 8-bit operands are multiplied to yield

a 16-bit product. The input can be registered in pipeline

mode.

CAM Mode

The CAM block is a binary content address memory

that provides fast address searches by receiving data

input and returning addresses that contain the data.

Implemented in each EBR are two 16-word x 8-bit CAM

function blocks.

The CAM has three modes, single match, multiple

match and clear, which are all achieved in one clock

cycle. In single match mode, a 8-bit data input is inter-

nally decoded and reports a match when data is

present in a particular RAM address. Its result is

reported by a corresponding single address bit. In mul-

tiple match the same occurs with the exception of multi-

ple address lines report the match. Clear mode is used

to clear the CAM contents by erasing all locations one

cycle per location. The EBR blocks in CAM mode may

be cascaded to produce larger CAMs.

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