OR4 datasheet(80/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Propagation Delay—The time between the specified reference points. The delays provided are the worst case of

the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state

enable.

Setup Time—The interval immediately preceding the transition of a clock or latch enable signal, during which the

data must be stable to ensure it is recognized as the intended value.

Hold Time—The interval immediately following the transition of a clock or latch enable signal, during which the

data must be held stable to ensure it is recognized as the intended value.

3-State Enable—The time from when a 3-state control signal becomes active and the output pad reaches the

high-impedance state.

Table 39. PFU Timing Parameters

OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C

OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C

Note:

A complete listing of PFU Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.

Parameter

Symbol

Speed

Unit

–1

–2

–3

Min Max Min Max

Min

Max

Combinatorial Delays:

Four-input Variables to LUT out

Five-input Variables to LUT out

Six-input Variables to LUT out

F4_DEL

F5_DEL

F6_DEL

—

0.66

0.77

1.10

—

0.55

0.64

0.81

—

0.50

0.58

0.74

Sequential Delays:

CLK Low Time

CLK High Time

Four-input Variables to Register CLK setup

Five-input Variables to Register CLK setup

Six-input Variables to Register CLK setup

Data In to Register CLK setup

Four-input Variables from Register CLK hold

Five-input Variables from Register CLK hold

Six-input Variables from Register CLK hold

Data In from Register CLK hold

CLKL_MPW

CLKH_MPW

F4_SET

F5_SET

F6_SET

DIN_SET

F4_HLD

F5_HLD

F6_HLD

DIN-HLD

REG_DEL

0.36

0.40

0.28

0.38

0.71

0.00

0.10

0.00

0.25

1.03

—

0.35

0.38

0.23

0.28

0.63

0.00

0.16

0.10

0.24

0.92

—

0.32

0.35

0.21

0.25

0.57

0.00

0.15

0.09

0.22

0.84

—

PFU CLK to Out (REG_DEL) Delay Adjustments

from Cycle Stealing:

One Delay Cell

Two Delay Cells

Three Delay Cells

CYCDEL1

CYCDEL2

CYCDEL3

0.89

1.64

2.43

—

0.70

1.29

1.98

—

0.64

1.18

1.80

—

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