OR4 datasheet(44/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Special Function Blocks (continued)

5-5768(F).b

Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram

TAP

CONTROLLER

TMS

TCK

BOUNDARY-SCAN REGISTER

ISC READ/WRITE REGISTERS

BYPASS AND ISC_DEFAULT REGISTER

DATA

MUX

INSTRUCTION DECODER

INSTRUCTION REGISTER

RESET

CLOCK IR

SHIFT-IR

UPDATE-IR

PUR

TDO

SELECT

ENABLE

RESET

CLOCK DR

SHIFT-DR

UPDATE-DR

TDI

DATA REGISTERS

PSR1,PSR2,PSR3 REGISTERS (PLCs)

CONFIGURATION REGISTER

(RAM_R, RAM_W)

PRGM

I/O BUFFERS

VDD

IDCODE/USER CODE REGISTER

ORCA Series TAP Controller (TAPC)

The ORCA Series TAP controller (TAPC) is a 1149

compatible test access port controller. The 16 JTAG

state assignments from the IEEE 1149 speciﬁcation

are used. The TAPC is controlled by TCK and TMS. The

TAPC states are used for loading the IR to allow three

basic functions in testing: providing test stimuli

(Update-DR), test execution (Run-Test/Idle), and

obtaining test responses (Capture-DR). The TAPC

allows the test host to shift in and out both instructions

and test data/results. The inputs and outputs of the

TAPC are provided in the table below. The outputs are

primarily the control signals to the instruction register

and the data register.

Table 20. TAP Controller Input/Outputs

Symbol

I/O

Function

TMS

Test Mode Select

TCK

Test Clock

PUR

Powerup Reset

PRGM

BSCAN Reset

TRESET

O Test Logic Reset

Select

O Select IR (High); Select-DR (Low)

Enable

O Test Data Out Enable

Capture-DR

O Capture/Parallel Load-DR

Capture-IR

O Capture/Parallel Load-IR

Shift-DR

O Shift Data Register

Shift-IR

O Shift Instruction Register

Update-DR

O Update/Parallel Load-DR

Update-IR

O Update/Parallel Load-IR

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