OR4 datasheet(42/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Special Function Blocks (continued)

The external test (EXTEST) instruction allows the inter-

connections between ICs in a system to be tested for

opens and stuck-at faults. If an EXTEST instruction is

performed for the system shown in Figure 25, the con-

nections between U1 and U2 (shown by nets a, b,

and c) can be tested by driving a value onto the given

nets from one device and then determining whether

this same value is seen at the other device. This is

determined by shifting 3 bits of data for each pin (one

for the output value, one for captured input value, and

one for the 3-state value) through a boundary scan reg-

ister (BSR) until each one aligns to the appropriate pin.

Then, based upon the value of the 3-state data bit for

each pin, either the I/O pad is driven to the value given

in the output register of the BSR, or an input signal is

applied at the pin. In either case, the BSR input register

is updated with the input value from the I/O pad, which

allows it to be shifted out TDO. Typically, the user will

use the PRELOAD instruction to shift in the ﬁrst test

stimulus for the EXTEST instruction. Note that Series 4

boundary scan includes the ability to perform a self-

monitor on each I/O pin by driving out a value from the

output register and checking for this value at the input

The SAMPLE instruction is useful for system debug-

ging and fault diagnosis by allowing the data at the

FPGA’s I/Os to be observed during normal operation.

The data for all of the I/Os is captured simultaneously

into the BSR, allowing them to be shifted-out TDO to

the test host. Since each I/O buffer in the PIOs is bidi-

rectional, two pieces of data are captured for each I/O

pad: the value at the I/O pad and the value of the 3-

state control signal.

The PRELOAD instruction is used to allow the scan-

ning of the boundary-scan register without causing

interference to the normal operation of the on-chip sys-

tem logic. In turn it allows an initial data pattern to be

placed at the latched parallel outputs of BSR prior to

selection of another boundary scan test operation. For

example, prior to selection of the EXTEST instruction,

data can be loaded onto the latched parallel outputs

using PRELOAD. As soon as the EXTEST instruction

has been transferred to the parallel output of the

instruction register, the preloaded data is driven

through the system output pins. This ensures that

known data, consistent at the board level, is driven

immediately when the EXTEST instruction is entered.

Without PRELOAD, indeterminate data would be

driven until the ﬁrst scan sequence had been com-

pleted.

There are six ORCA-deﬁned instructions. The PLC

scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user-

deﬁned internal scan paths using the PLC latches/FFs

and routing interface. The RAM_Write Enable

(RAM_W) instruction allows the user to serially conﬁg-

ure the FPGA through TDI. The RAM_Read Enable

(RAM_R) allows the user to read back RAM contents

on TDO after conﬁguration. The IDCODE instruction

allows the user to capture a 32-bit identiﬁcation code

that is unique to each device and serially output it at

TDO. The IDCODE format is shown in Table 19.

An optional IEEE 1149.3 instruction RUNBIST has

been implemented. This instruction is used to invoke

the built in self test (BIST) of regular structures like

RAMs, ROMs, FIFOs, etc., and the surrounding ran-

dom logic in the circuit.

The USERCODE instruction shifts out a 32-bit ID seri-

ally at TDO. At powerup, a default value of the IDCODE

with the manufacturer ﬁeld (11-bits) set to all zeros is

loaded. The user can set this 11-bit value to a user-

deﬁned number during device conﬁguration. It may

also be changed by the ISC_PROGRAM_USERCODE

instruction, described later.

Also implemented in Series 4 devices is the IEEE

1532/D1 standards for in-system conﬁguration for pro-

grammable logic devices. Included are 4 mandatory

and 2 optional instructions deﬁned in the standards.

ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and

ISC_DISABLE are the four mandatory instructions.

ISC_ENABLE initializes the devices for all subsequent

ISC instructions. The ISC_PROGRAM instruction is

similar to the RAM_WRITE instruction implemented in

all ORCA devices where the user must monitor the

PINITN pin for a high indicating the end of initialization

and a successful conﬁguration can be started. The

ISC_PROGRAM instruction is used to program the

conﬁguration memory through a dedicated ISC_Pdata

gramming multiple devices in parallel. During this mode

TDI and TDO behave like BYPASS. The data shifted

through TDI is shifted out through TDO. However the

output pins remain in control of the BSR unlike

BYPASS where they are driven by the system logic.

The ISC_DISABLE is used upon completion of the ISC

programming. No new ISC instructions will be operable

without another ISC_ENABLE instruction.

Optional 1532/D1 instructions include

ISC_PROGRAM_USERCODE. When this instruction is

loaded, the user shifts all 32-bits of a user-deﬁned ID

(LSB ﬁrst) through TDI. This overwrites any ID previ-

ously loaded into the ID register. This ID can then be

read back through the USERCODE instruction deﬁned

in IEEE 1149.2.

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