OR4 datasheet(64/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Conﬁguration Data Format (continued)

The number of frames, number of bits/frame, total number of bits and the required PROM size for each Series 4

device is shown in Table 32

Table 32. Conﬁguration Frame Size

Bit Stream Error Checking

There are three different types of bit stream error checking performed in the ORCA Series 4 FPGAs:

ID frame, frame alignment, and CRC checking.

The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device

for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are

ﬂagged as an ID error. This frame is automatically created by the bit stream generation program in ispLEVER.

Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to

1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is ﬂagged as a frame alignment

error.

Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-

uation of the checksum byte, then a checksum/parity error is ﬂagged. The checksum is the XOR of all the data

bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and

data frames.

When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will

remain in this state until either the RESET or PRGM pins are asserted The PGRM bits of the MPI control register can

also be used to reset out of the error condition and restart conﬁguration.

If using any of the MPI modes to conﬁgure the FPGA, the speciﬁc type of bit stream error is written to one of the

MPI

registers by the FPGA conﬁguration logic. This same information can also be read from the data register when

in asynchronous peripheral mode.

FPGA Conﬁguration Modes

There are twelve methods for conﬁguring the FPGA as show in Table 33. Eleven of the conﬁguration modes are

selected on the M0, M1, M2, and M3 inputs. The twelfth conﬁguration mode is accessed through the boundary-

scan interface. Some modes are used to select the frequency of the internal oscillator, which is the source for

CCLK in some conﬁguration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz.

There are three basic FPGA conﬁguration modes: master, slave, and peripheral which includes MPI mode. The

conﬁguration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the

control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK

input. In the ﬁve peripheral modes, the FPGA acts as a microprocessor peripheral. Table 33 lists the functions of

the conﬁguration mode pins.

Devices

OR4E02

OR4E04

OR4E06

Number of Frames

1796

2436

3076

Data Bits/Frame

900

1284

1540

Maximum Conﬁguration Data (Number of bits/frame x Number of frames) 1,616,400

3,127,824

4,737,040

Maximum PROM Size (bits) (add conﬁguration header and postamble)

1,616,648

3,128,072

4,737,288

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