OR4 datasheet(72/152 Pages) LATTICE

72 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA Conﬁguration Modes (continued)

Slave Serial Mode

The slave serial mode is primarily used when multiple FPGAs are conﬁgured in a daisy-chain (see the Daisy-

Chaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in

the slave serial mode can be used as the lead device in a daisy-chain. Figure 44 shows the connections for the

slave serial conﬁguration mode.

The conﬁguration data is provided into the FPGA’s DIN input synchronous with the conﬁguration clock CCLK input.

After the FPGA has loaded its conﬁguration data, it retransmits the incoming conﬁguration data on DOUT at the ris-

ing edge of CCLK. CCLK is routed into all slave serial mode devices in parallel.

Multiple slave FPGAs can be loaded with identical conﬁgurations simultaneously. This is done by loading the con-

ﬁguration data into the DIN inputs in parallel.

5-4485(F).a

Figure 44. Slave Serial Conﬁguration Schematic

Slave Parallel Mode

The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins

D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a

valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a

daisy-chain conﬁguration.

Figure 45 is a schematic of the connections for the slave parallel conﬁguration mode. WR and CS0 are active-low

chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to conﬁgure mul-

tiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can

then be used to select the FPGAs to be conﬁgured with a given bit stream. The chip selects must be active for each

valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must

meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the

microprocessor only if a standard prom ﬁle format is used. If a .bit or .rbt ﬁle is used from ispLEVER, then the user

must mirror the bytes in the .bit or .rbt ﬁle OR leave the .bit or .rbt ﬁle unchanged and connect D[7:0] of the FPGA

to D[0:7] of the microprocessor.

MICRO-

PROCESSOR

DOWNLOAD

CABLE

HDC

SERIES

FPGA

LDC

VDD

CCLK

PRGM

DOUT

TO DAISY-

CHAINED

DEVICES

DONE

DIN

INIT

ORCA

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