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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OR4 датащи(PDF) 103 Page - Lattice Semiconductor |
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OR4 датащи(HTML) 103 Page - Lattice Semiconductor |
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103 / 152 page  Lattice Semiconductor 103 Data Sheet May, 2006 ORCA Series 4 FPGAs Pin Information (continued) Table 65. Pin Descriptions (continued) Symbol I/O Description Special-Purpose Pins (continued) WR/MPI_RW I WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA. In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to the FPGA. I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.* PPC_A[14:31] I During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least-significant bits of the PowerPC 32-bit address. MPI_BURST IMPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates that the current transfer is not a burst. MPI_BDIP IMPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[0:1] I MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. A[21:0] O During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_ACK O In MPI mode this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_CLK I This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used this will be the AMBA bus clock. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_TEA O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_RTRY O This pin requests the MPC860 to relinquish the bus and retry the cycle. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* D[0:31] I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction. I D[7:0] receive configuration data during master parallel, peripheral, and slave parallel config- uration modes when WR is low and each pin has a pull-up enabled. During serial configura- tion modes, D0 is the DIN input. O D[7:3] output internal status for asynchronous peripheral mode when RD is low. I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.* DP[0:3] I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:31]. After configuration, if MPI is not used, the pins are user-programmable I/O pin.* * The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. |
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