STLC1502 datasheet(56/81 Pages) STMICROELECTRONICS

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here below, where the D950 sends a message to the ARM. The same apply in the reverse direction with ARM

and D950 side swapped.

•

The D950 reads the D950 MAILBOX register bit corresponding to the channel it wants use for the

message. If it is set to 1, the previous message has not been read by the ARM and the channel is not

available. If the content of that bit is 0, then the D950 can write the message for the ARM into the

appropriate section of the DPRAM

•

The D950 writes any value in the appropriate D950_STATUS_X location (0<= X<= 15), indicating

that the message has just been put in the DPRAM. This will cause the corresponding bit in the D950

MAILBOX register to be set to 1.

•

If the corresponding bit in the D950 Mailbox Mask register is set to 1, then an interrupt request for the

ARM will be generated. The interrupt line is the logical OR of all the unmasked bits in the D950 MAIL-

BOX register.

•

The ARM interrupt service routine will read the D950 MAILBOX register and compare this with the

D950 Mailbox MASK register to determine which channel caused the interrupt.

•

The ARM reads the appropriate section of the DPRAM. When it has finished reading the message, it

reads the corresponding D950 STATUS location.

•

This latest read clears the corresponding bit in the D950 MAILBOX register. If no other unmasked

bits are set in the D950 MAILBOX register, the ARM interrupt clears, otherwise remains set.

•

Multiple channels can be used concurrently. It is up to the receiver to manage this eventuality. So the

DPRAM can be used to buffer the messages as it is processed, while other channels are still availa-

ble for communication.

7.10.2 Dual Port memory map [0x0C180000]

The base address of the Dual Port memory is 0x0C180000.

The base address of control registers is 0x0C188000

The DPRAM is mapped in the ARM memory space as shown below:

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