STLC1502 datasheet(40/81 Pages) STMICROELECTRONICS

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STLC1502

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Int.Base + 0x0C

IRQSoft

R/W

Only the bit 1 has to be used.

Writing ‘1’ it generates an inter-

rupt mapped in the bit 1 of the

IRQStatus and of the IRQRaw-

Status registers. Writing ‘0’ the

software

interrupt

cause

erased.

Int.Base + 0x10

FIQStatus

For the FIQ interrupt cause, ‘1’

means an active pending inter-

rupt that has to be served by

the ARM.

Int Base + 0x14

FIQRawStatus

For the IRQ interrupt source, a

‘1’ means an active pending

interrupt “before” the mask (w/

o considering the mask)

Int.Base + 0x18

FIQEnableSet

R/W

For the FIQ interrupt source, a

‘0’ means that even if an inter-

rupt source is active, it has to

stopped

(masked).

The

write operation of 1 to the bit0,

enables the interrupt

Int.Base + 0x1C

IRQEnableClear

The write operation of 1 to a

given bit, disables the corre-

sponding interrupt. As conse-

quence, the corresponding bit

in the IRQEnableSet goes to 0

(interrupt disabled).

Int.Base + 0x20

FIQEnableClear

The write operation of 1 into

the bit 0 disables FIQ interrupt

cause. As a result, the bit 0 in

the FIQEnableSet goes to 0

(interrupt disabled).

Int.Base + 0x24

IRQTestSource

R/W

Usable when the bit 0 of the

IRQSourceSel is set to one. In

this case this register is the

interrupt source cause. If set,

the cause is active (interrupt

generated) while if reset, the

cause is not active.

Address

R/W

Notes

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