STLC1502 datasheet(13/81 Pages) STMICROELECTRONICS

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STLC1502

A scheme of the ESM control interface is reported in Figure 5.

Figure 5: ESM control interface

Every CS space can be programmed through internal register (one for each CS) in order to:

•

select the number of wait states to perform external access depending on the speed of the external

device mapped on that memory area

•

select if the data bus is x8 or x16 (available only for CS1 to CS2). When the x8 memories are used,

their data bus has to be placed on the ESM_D(7:0) signals

The wait states number for the external memories (depending on memory access time) is obtained from the

software code during the download phase. During the initialization phase, it is the responsibility of the software

to determine if a SRAM or a FLASH is present or not on a given CS space and the width of CS1-2 memories (if

WE[3:0]

OUT

Bytes Write enable. They are

used to select one/two bytes

when a x16/x32 Flash/SRAM is

present (shared with EDM).

0: lower byte

1: 2nd byte

2: 3rd byte

3: higher byte

ESM_CS0WIDTH

This input informs whether a x8

(ESM_CS0WIDTH=0)

x16

(ESM_CS0WIDTH=1) device is

present on the CS0. This informa-

tion is needed the boot from exter-

nal memory is selected.

A[21:0]

OUT

Address

lines

for

4Mbytes address space (shared

with EDM A[13:0])

D[31:0]

INOUT

Data bus(shared with EDM bus)

NAME

Signal type

Description

ESM_CS(2:0)

WE[3:0]

external side

device side

ESM_CS0WIDTH

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