MCP4725 datasheet(14/42 Pages) MICROCHIP

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MCP4725

DS22039C-page 14

5.0

GENERAL DESCRIPTION

The MCP4725 is a single channel buffered voltage

output

12-bit

DAC

with

non-volatile

memory

(EEPROM). The user can store configuration register

bits (2 bits) and DAC input data (12 bits) in non-volatile

EEPROM (14 bits) memory.

When the device is powered on first, it loads the DAC

code from the EEPROM and outputs the analog output

accordingly with the programmed settings. The user

can reprogram the EEPROM or DAC register any time.

The device uses a resistor string architecture. DAC’s

output is buffered with a low power precision amplifier.

This output amplifier provides low offset voltage and

low noise, as well as rail-to-rail output. The amplifier

can also provide high source currents (VOUT pin to

VSS).

The DAC can be configured to normal or power saving

power-down mode by setting the configuration register

bits.

The device uses a two-wire I2C compatible serial

interface and operates from a single power supply

ranging from 2.7V to 5.5V.

5.1

Output Voltage

The input coding to the MCP4725 device is unsigned

binary. The output voltage range is from 0V to VDD. The

output voltage is given in Equation 5-1:

EQUATION 5-1:

5.1.1

OUTPUT AMPLIFIER

The DAC output is buffered with a low-power, precision

CMOS amplifier. This amplifier provides low offset

voltage and low noise. The output stage enables the

device to operate with output voltages close to the

power supply rails. Refer to

Section 1.0 “Electrical

Characteristics” for range and load conditions.

The output amplifier can drive the resistive and high

capacitive loads without oscillation. The amplifier can

provide maximum load current as high as 25 mA which

is enough for most of a programmable voltage

reference applications.

5.1.2

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The MCP4725 output stage is capable of driving loads

up to 1000 pF in parallel with 5 k

Ω load resistance.

Figure 2-15 shows the VOUT vs. Resistive Load. VOUT

drops slowly as the load resistance decreases after

about 3.5 k

Ω.

5.2

LSB SIZE

One LSB is defined as the ideal voltage difference

between two successive codes. (see Equation 4-1).

Table 5-1 shows an example of the LSB size over

full-scale range (VDD).

TABLE 5-1:

LSB SIZES FOR MCP4725

(EXAMPLE)

5.3

Voltage Reference

The MCP4725 device uses the VDD as its voltage

reference. Any variation or noises on the VDD line can

affect directly on the DAC output. The VDD needs to be

as clean as possible for accurate DAC performance.

5.4

Reset Conditions

In the Reset conditions, the device uploads the

EEPROM data into the DAC register. The device can

be reset by two independent events: (a) by POR or (b)

by I2C General Call Reset Command.

The factory default settings for the EEPROM prior to

shipment are shown in Table 4-3 (set for a middle scale

output). The user can rewrite or read the DAC register

or EEPROM anytime after the Power-On-Reset event.

5.4.1

POWER-ON-RESET

The device’s internal Power-On-Reset (POR) circuit

ensures that the device powers up in a defined state.

If the power supply voltage is less than the POR thresh-

old (VPOR = 2V, typical), all circuits are disabled and

there will be no DAC output. When the VDD increases

above the VPOR, the device takes a reset state. During

the reset period, the device uploads all configuration

and DAC input codes from EEPROM. The DAC output

will be the same as for the value last stored in the

EEPROM. This enables the device returns to the same

state that it was at the last write to the EEPROM before

it was powered off.

OUT

REF

()

4096

-------------------------------

Where:

VREF

=VDD

Input code

Full-Scale

Range

(VDD)

LSB

Size

Condition

3.0V

0.73 mV

3 / 4096

5.0V

1.22 mV

5 / 4096

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