MCP4725 datasheet(10/42 Pages) MICROCHIP

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MCP4725

DS22039C-page 10

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

Analog Output Voltage (V

OUT)

VOUT is an analog output voltage from the DAC device.

DAC output amplifier drives this pin with a range of VSS

to VDD.

3.2

Supply Voltage (V

DD, VSS)

VDD is the power supply pin for the device. The voltage

at the VDD pin is used as the supply input as well as the

DAC reference input. The power supply at the VDD pin

should be clean as possible for a good DAC

performance.

This pin requires an appropriate bypass capacitor of

about 0.1 µF (ceramic) to ground. An additional 10 µF

capacitor (tantalum) in parallel is also recommended to

further attenuate high frequency noise present in

application boards. The supply voltage (VDD) must be

maintained in the 2.7V to 5.5V range for specified

operation.

VSS is the ground pin and the current return path of the

device. The user must connect the VSS pin to a ground

plane through a low impedance connection. If an

analog ground path is available in the application PCB

(printed circuit board), it is highly recommended that

the VSS pin be tied to the analog ground path or isolated

within an analog ground plane of the circuit board.

3.3

Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA

pin is used to write or read the DAC register and

EEPROM data. The SDA pin is an open-drain N-chan

nel driver. Therefore, it needs a pull-up resistor from the

VDD line to the SDA pin. Except for start and stop

conditions, the data on the SDA pin must be stable

during the high period of the clock. The high or low

state of the SDA pin can only change when the clock

signal on the SCL pin is low. Refer to

Section 7.0 “I2C

Serial Interface Communication” for more details of

I2C Serial Interface communication.

3.4

Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The

MCP4725 acts only as a slave and the SCL pin accepts

only external serial clocks. The input data from the

Master device is shifted into the SDA pin on the rising

edges of the SCL clock and output from the MCP4725

occurs at the falling edges of the SCL clock. The SCL

pin is an open-drain N-channel driver. Therefore, it

needs a pull-up resistor from the VDD line to the SCL

pin. Refer to

Section 7.0 “I2C Serial Interface Com-

munication” for more details of I2C Serial Interface

communication.

3.5

Device Address Selection Pin (A0)

This pin is used to select the A0 address bit by the user.

The user can tie this pin to VSS (logic ‘0’), or VDD (logic

‘1’), or can be actively driven by the digital logic levels,

such as the I2C Master Output. See

Section 7.2

“Device Addressing” for more details of the address

bits.

TABLE 3-1:

PIN FUNCTION TABLE

Pin No.

SOT-23

Name

Function

1VOUT

Analog Output Voltage

2VSS

Ground Reference

3VDD

Supply Voltage

4SDA

I2C Serial Data

5SCL

I2C Serial Clock Input

Device Address Selection pin. This pin can be tied to VSS or VDD, or can be actively

driven by the digital logic levels. The logic state of this pin determines what the A0

bit of the I2C address bits should be.

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