MCP4725 datasheet(22/42 Pages) MICROCHIP

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MCP4725

DS22039C-page 22

7.3

General Call

The MCP4725 device acknowledges the general call

address (0x00 in the first byte). The meaning of the

general call address is always specified in the second

byte (see Figure 7-2). The I2C specification does not

allow to use “00000000” (00h) in the second byte.

Please refer to the Phillips I2C document for more

details

the

General

Call

specifications.

The

MCP4725 supports the following general calls:

7.3.1

GENERAL CALL RESET

The general reset occurs if the second byte is

“00000110” (06h). At the acknowledgement of this

byte, the device will abort current conversion and

perform an internal reset similar to a power-on-reset

(POR). Immediately after this reset event, the device

uploads the contents of the EEPROM into the DAC

7.3.2

GENERAL CALL WAKE-UP

If the second byte is “00001001” (09h), the device will

reset the power-down bits. After receiving this com-

mand, the power-down bits of the DAC register are set

to a normal operation (PD1, PD2 = 0,0). The

power-down bit settings in EEPROM are not affected.

FIGURE 7-2:

General Call Address

Format.

7.4

High-Speed (HS) Mode

The I2C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

(3.4 Mbit/s) mode. This is done by sending a special

address byte of 00001XXX following the START bit.

The XXX bits are unique to the high-speed (HS) mode

Master. This byte is referred to as the high-speed (HS)

Master Mode Code (HSMMC). The MCP4725 device

does not acknowledge this byte. However, upon

receiving this command, the device switches to HS

mode and can communicate at up to 3.4 Mbit/s on SDA

and SCL lines. The device will switch out of the HS

mode on the next STOP condition.

For more information on the HS mode, or other I2C

modes, please refer to the Phillips I2C specification.

7.5

I2C BUS CHARACTERISTICS

The I2C specification defines the following bus

protocol:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined using Figure 7-3.

7.5.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

7.5.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START

condition.

7.5.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

7.5.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition.

LSB

First Byte

ACK

0 A

x x x

x x

(General Call Address)

Second Byte

ACK

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