MK50H27PLCC datasheet(36/56 Pages) STMICROELECTRONICS

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4.3.2 Transmit Message Descriptor Entry

4.3.2.1 Transmit Message Descriptor 0 (TMD0)

BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero either the HOST or the SLAVE PROCESSOR

owns this descriptor. When this bit is a one the MK50H27 owns this

descriptor.

The host sets the OWNA bit after filling the buffer pointed

to by the descriptor entry. The MK50H27 releases the descriptor after

transmitting

the buffer

and

receiving

the

proper acknow-

ledgement from the receiver. After the MK50H27, Host, or I/O ac-

celeration processor has relinquished ownership of a buffer, it may not

change any field in the four words that comprise the descriptor entry.

OWNB

This bit determines whether the Host or the Layer 3 I/O Processor owns

the buffer when OWNA is a zero.

The MK50H27 never uses this

bit. This bit is provided to facilitate use of a Layer 3 I/O processor.

SLF

Start of Long Signal Unit indicates that this is the first buffer used by the

MK50H27 for this signal unit. It is used for data chaining buffers. SLF

is set by the Host. When not chaining, SLF should be set to a one.

NOTE: A ”Long Signal Unit” is any MSU which needs data chaining.

ELF

End of Long Signal Unit indicates that this is the last buffer used by the

MK50H27 for this signal unit. It is used for data chaining buffers. If

both SLF and ELF were set the signal unit would fit into one buffer

and no data chaining would be required. ELF is set by the

Host.

When not chaining, ELF should be set to a one.

11:08

Reserved, must be written as zeroes for CCITT/ITU operation.

11:10

PRIN

These bits determine the content of the Priority Indication bits of the

transmitted frame when JSS7E=1 (TTC JT-Q703 compliant mode).

07:00

TBADR

The High Order 8 address bits of the buffer pointed to by this descriptor.

This field is written by the Host and unchanged by MK50H27.

4.3.2.2 Transmit Message Descriptor 1 (TMD1)

BIT

NAME

DESCRIPTION

15:00

TBADR

The Low Order 16 address bits of the buffer pointed to by this descriptor

TBADR is written by the Host and unchanged by MK50H27.

The

least significant bit is zero since the descriptor must be word aligned.

TBADR<15:00>

TBADR<23:16>

PRIN

MK50H27

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