MK50H27PLCC datasheet(34/56 Pages) STMICROELECTRONICS

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4.3 Receive and Transmit Descriptor Rings

Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit

descriptors.

4.3.1 Receive Message Descriptor Entry

4.3.1.1 Receive Message Descriptor 0 (RMD0)

BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero either the HOST or the I/O ACCELERATION

PROCESSOR owns this descriptor.

When this bit is

one

the

MK50H27 owns this descriptor. The chip clears the OWNA bit af-

ter filling the buffer pointed to by the descriptor entry provided a valid

signal unit has been received. The Host sets the OWNA bit after

emptying the buffer. Once the MK50H27, Host, or I/O accelera-

tion processor has relinquished ownership of

a buffer, it may not

change any field in the four words that comprise the descriptor entry.

OWNB

This bit determines whether the Host or the Layer 3 I/O Processor owns

the buffer when OWNA is a zero.

The MK50H27 never uses this

bit. This bit is provided to facilitate use of a Layer 3 I/O processor.

SLF

Start of Long Signal Unit indicates that this is the first buffer used

by MK50H27 for this signal unit. It is used for data chaining buffers.

SLF is set by the MK50H27. NOTE: A ”Long Signal Unit” is any

MSU which needs data chaining.

ELF

End of Long Signal Unit indicates that this the last buffer used by

MK50H27 for this signal unit. It is used for data chaining buffers. If

both SLF and ELF were set, the signal unit would fit into one buffer

and no data chaining would be required. ELF is set by the MK50H27.

11:08

Reserved, must be written as zeroes for CCITT/ITU compliant operation.

11:10

PRIN

These bits indicate the content of the Priority Indication bits of the

received frame when JSS7E=1 (TTC JT-Q703 compliant mode).

07:00

RBADR

The High Order 8 address bits of the buffer pointed to by this descriptor.

This field is written by the Host and unchanged by MK50H27.

RBADR<23:16>

PRIN

MK50H27

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