MK50H27PLCC datasheet(22/56 Pages) STMICROELECTRONICS

22 / 56 page

”Non-data DMA transfers refers to any DMA transfers that access

memory other than the data buffers themselves. This includes the

Initialization

Block, Descriptors, and Status Buffer. It has no effect

on data DMA transfers. BSWPC allows the MK50H27 to operate with

memory organizations that have bits 07:00 at even addresses and

with bits 15:08 at

odd

addressses

vice versa.

BSWPC is

Read/Write and cleared by BUS RESET.

With BSWPC = 1:

Address

This memory organization is used with the 8086 family of microproces-

sors.

With BSWPC = 0:

Address

This memory organization is used with the 68000

and

the Z8000

microprocessors.

04:03

BURST

This field determines the maximum number of data transfers

performed each time control of the host bus is obtained. BURST

is READ/WRITE and cleared on bus Reset.

* Suggested setting

BSWPD

This bit determines the byte ordering of all data DMA transfers.

Data transfers are those to or from a data buffer. BSWPD has no ef-

fect on non-data transfers. The effect of BSWPD on data transfers is

the same

that

BSWPC on non-data transfers

(see

above).

For most applications, including most 68000 based sys-

tems, this bit should be set.

ACON

ALE CONTROL defines the assertive state of pin 18 when the

MK50H27 is a Bus Master. ACON is READ/ WRITE and cleared by

Bus RESET.

BCON

BYTE CONTROL redefines the Byte Mask and Hold I/O pins.

BCON is READ/WRITE and cleared by Bus RESET.

BURST <1:0>

8 bit mode

16 bit mode

2 bytes

1 words

10*

16 bytes

8 words

unlimited

...

XX0

XX1

. . .

8. . .

XX1

. . .

ACON

PIN18

NAME

ASSERTED HIGH

ALE

ASSERTED LOW

BCON

PIN16

PIN15

PIN17

BM1

BM0

HOLD

BUSAKO

BYTE

BUSRQ

MK50H27

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