MK50H27PLCC datasheet(33/56 Pages) STMICROELECTRONICS

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4.2.7 Reserved

BIT

NAME

DESCRIPTION

15:00

Reserved, must be written as zeroes.

4.2.8 Statistics

A significant portion of the initialization buffer is reserved for statistical information collected by the

MK50H27. When a statistic is updated, the MK50H27 will read the appropriate statistic, increment it,

and then write it back out to memory. These statistics are intended for the use of the Host CPU for

statistical analysis. The MK50H27 will only increment these counters; it is up to the user to clear and

preset these counters. The statistics collected are:

Memory Address

Error Counter

IADR + 50

SL Failure - number of link failures due to abnormal FIB/BSN received.

IADR + 52

SL Failure - number of link failures due to excessive delays of

acknowledgement caused by timer T7 time out.

IADR + 54

SL Failure - number of link failures due to excessive SUERM error rate.

IADR + 56

SL Failure - number of link failures due to excessive congestion

caused by timer T6 time out.

IADR + 58

Number of alignment failures due to timers T2 or T3 timing out.

IADR + 60

Number of alignment failues due to AERM exceeded.

IADR + 62

Number of negative acknowledgements received.

IADR + 64

Number of Signal Units in error.

IADR + 66 - 122

Reserved. Must be programmed as zeroes.

IADR + 124

Number of SIB’s transmitted.

IADR + 126

Number of SIB’s received.

IADR + 128

Number of forced retransmissions caused by N1.

IADR + 130

Number of forced retransmissions caused by N2.

IADR + 132

Number of MSU’s retransmitted.

IADR + 134

Number of MSU octets retransmitted. This value includes the opening

and closing flags, BSN/BIB, FSN/FIB, LI, and the CK octets.

IADR + 136 - 198

Reserved. Must be programmed as zeroes.

Note:

IADR+144 - 151

Used for TTC JT-Q703 compliant timers Tf, Ts, To, and Ta if JSS7E=1.

See page 27 for details.

IADR + 48

RESERVED

MK50H27

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