CHR71000 datasheet(10/54 Pages) AMSOSRAM

10 / 54 page

CHR71000

Pin assignment

Datasheet • PUBLIC • Document Feedback

DS000427 • v2-01 • 2026-Mar-18

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Pin number

Pin name

Description

Remarks

E12

CMD_OUT1

Bias setting output amp 1

(CDS/PGA)

Connect to 100nF capacitor to

GND (or force bias voltage(1))

E13

CMD_OUT2

Bias setting output amp 2 (output

buffer)

Connect to 100nF capacitor to

GND (or force bias voltage(1))

VDD_TRANSFER

Power supply for the transfer pixel

lines

Peak current at start up(2), 10mA

peak normal operation (all pins)

VDD_RESET

Power supply for the reset pixel

lines

Peak current at start up(2), 10mA

peak normal operation (all pins)

GNDAB

Anti-blooming supply (reset and

transfer low level)

Sink current, max. 10mA (all pins).

Can be tied to analog ground.

EOS_Y_L_READ

EOS from left read shift register in

y direction

Not used. Do not connect.

EOS_Y_L_INTE

EOS from left integration shift

Not used. Do not connect.

VDD_PIX

Pixel array power supply

Has large peak currents during

RBT

GND

0V reference

EOS_Y_R_INTE

EOS from right integration shift

Not used. Do not connect.

EOS_Y_R_READ

EOS from right read shift register

in y direction

Not used. Do not connect.

M10

CMD_COL3

Bias setting column load 1 (ctu)

Connect to 100nF capacitor to

VDD_PIX (or force bias voltage(1))

M11

CMD_COL4

Bias setting column load 2

(precharge)

Connect to 100nF capacitor to

VDD_PIX (or force bias voltage(1))

M12

VDD_PIX

Pixel array power supply

Peak currents during RBT

M13

GND

0V reference

(1) Bias signals generated on-chip, forced outside if needed.

(2) Possibly large peak current at start-up; may be limited by resistance to pin or slower ramp-up

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