CHR71000 datasheet(29/54 Pages) AMSOSRAM

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CHR71000

Functional description

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7.3.2.2

Using the internal sequencer

When using the internal sequencer, all image core signals are generated on the chip. The only

digital inputs that need to be driven when using the sequencer are CLK_IN, RESET_N,

SEQ_START and SEQ_STOP. The SEQ_START is pulsed to initiate a frame transfer and

SEQ_STOP can be used to stop a frame transfer before it is finished. The rest of the timing is

controlled through register upload. The internal sequencer is enabled by writing a '1' to the

The most important properties that are controlled through register upload are:

•

The number of frames that are grabbed after a pulse on SEQ_START. (Set by register

reg_nrof_frames[15:0]. The range is 1 to 65535. If a value of 0 is uploaded, the sensor

sends out frames continuously until stopped by a pulse on SEQ_STOP).

•

The integration time (expressed as number of line times). (Set by register

reg_inte_time[23:0]. The range is 1 to 224-1. A value of 0 is invalid).

•

The window and sub-sampling settings. (Set with registers reg_addr_x_start[9:0],

reg_addr_y_start[9:0], reg_addr_x_end[9:0], reg_addr_y_end[9:0] and reg_sub_y. The

range of this registers has been discussed before).

The timing generated by the sequencer follows the timing as specified in previous section, with

a setting of 60 clock cycles for sample length and 30 clock cycles for transfer length

respectively.

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