| поискавой системы для электроныых деталей |
|
RA4M2 датащи(PDF) 42 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
RA4M2 датащи(HTML) 42 Page - Renesas Technology Corp |
|
42 / 93 page ![]() Note: 200 ns minimum in Software Standby mode. Note: If the clock source is switched, add 4 clock cycles of the switched source. Note 1. tPcyc indicates the PCLKB cycle. Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock. tNMIW NMI Figure 2.17 NMI interrupt input timing tIRQW IRQ Figure 2.18 IRQ interrupt input timing 2.3.6 I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing Table 2.22 I/O ports, POEG, GPT, AGT, and ADC12 trigger timing GPT32 Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. AGT Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width tPRW 1.5 — tPcyc Figure 2.19 POEG POEG input trigger pulse width tPOEW 3 — tPcyc Figure 2.20 GPT Input capture pulse width Single edge tGTICW 1.5 — tPDcyc Figure 2.21 Dual edge 2.5 — GTIOCxY output skew (x = 0 to 3, Y = A or B) Middle drive buffer tGTISK*1 — 4 ns Figure 2.22 High drive buffer — 4 GTIOCxY output skew (x = 4 to 7, Y = A or B) Middle drive buffer — 4 High drive buffer — 4 GTIOCxY output skew (x = 0 to 7, Y = A or B) Middle drive buffer — 6 High drive buffer — 6 OPS output skew GTOUUP, GTOULO, GTOVUP, GTOVLO, GTOWUP, GTOWLO tGTOSK — 5 ns Figure 2.23 AGT AGTIO, AGTEE input cycle tACYC*2 100 — ns Figure 2.24 AGTIO, AGTEE input high width, low width tACKWH, tACKWL 40 — ns AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 — ns ADC12 ADC12 trigger input pulse width tTRGW 1.5 — tPcyc Figure 2.25 Note: tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle. Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed. Note 2. Constraints on input cycle: RA4M2 Datasheet 2. Electrical Characteristics R01DS0367EJ0140 Rev.1.40 May 9, 2025 Page 42 of 93 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |