M7020R datasheet(118/150 Pages) STMICROELECTRONICS

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M7020R

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LEARN COMMAND

Bit [0] of each 68-bit data location specifies wheth-

er an entry in the database is occupied. If all the

entries in a device are occupied, the device as-

serts FULO signal to inform the downstream de-

vices that it is full.

The result of this communication between depth-

cascaded devices determines the global FULL

signal for the entire table. The FULL signal in the

last device determines the fullness of the depth-

cascaded table.

In a depth-cascaded table, only a single device will

learn the entry through the application of a LEARN

Instruction. The determination of which device is

going to learn is based on the FULI and FULO sig-

nalling between the devices. The first non-full de-

vice learns the entry by storing the contents of the

specified comparand registers to the location(s)

pointed to by NFA.

In a x68-configured table the LEARN command

writes a single 68-bit location. In a x136-config-

ured table the LEARN command writes the next

even and odd 68-bit locations. In 136-bit mode,

Bit[0] of the even and odd 68-bit locations is ’0,’

which indicates they are cascaded empty, or ’1,’

which indicates they are occupied.

The global FULL signal indicates to the Table Con-

troller (the host ASIC) that all entries within a block

are occupied and that no more entries can be

learned. The M7020R updates the signal after

each WRITE or LEARN command to a data array.

The LEARN command generates a WRITE cycle

to the external SRAM, also using the NFA register

as part of the SRAM address (see SRAM AD-

DRESSING, page 126).

The LEARN command is supported on a single

block containing up to eight devices if the table is

configured either as a x68 or a x136. The LEARN

command is not supported for x272-configured ta-

bles.

LEARN is a pipelined operation and lasts for two

CLK cycles, as shown in Figure 87, page 119

where TLSZ = 00, and Figure 88, page 120 and

Figure 89, page 121 where TLSZ = 01 (which as-

sume the device performing the LEARN operation

is not the last device in the table and has its LRAM

Bit set to ’0.’

Note: The OE_L for the device with the LRAM Bit

set goes high for two cycles for each LEARN (one

during the SRAM WRITE cycle, and one the cycle

before). The latency of the SRAM WRITE cycle

from the second cycle of the Instruction is shown

in Table 49, page 121.

The sequence of operation is as follows:

– Cycle 1A: The host ASIC applies the LEARN In-

struction on the CMD[1:0], using CMDV = 1.

The CMD[5:2] field specifies the index of the

comparand register pair that will be written in

the data array in the 136-bit-configured table.

For a LEARN in a 68-bit-configured table, the

even-numbered comparands specified by this

index will be written. CMD[8:7] carries the bits

that will be driven on SADR[21:20] in the SRAM

WRITE cycle.

– Cycle 1B: The host ASIC continues to drive

CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2]

with the comparand pair index. CMD[6] must be

set to '0' if the LEARN is being performed on a

68-bit-configured table, and to '1' if the LEARN

is being performed on a 136-bit-configured ta-

ble.

– Cycle 2: The host ASIC drives the CMDV to '0.'

At the end of Cycle 2, a new instruction can be-

gin. The latency of the SRAM WRITE is the

same as the search to the SRAM READ Cycle.

It is measured from the second cycle of the

LEARN Instruction.

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