CC113LRGPR datasheet(73/87 Pages) TI2

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parasitic

101

CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

6.3

Crystal

A crystal in the frequency range 26 - 27 MHz must be connected between the XOSC_Q1 and XOSC_Q2

pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors

(C81 and C101) for the crystal are required. The loading capacitor values depend on the total load

capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals

should equal CL for the crystal to oscillate at the specified frequency.

(9)

The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total

parasitic capacitance is typically 2.5 pF.

The crystal oscillator is amplitude regulated. This means that a high current is used to start up the

oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain

approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum.

The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see

Section 4.7).

The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet

the required frequency accuracy in a certain application.

Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal Q1

pad as this may shift the crystal dc operating point and result in duty cycle variation.

6.4

Reference Signal

The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This

input clock can either be a full-swing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-

peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be

connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal, this capacitor can

be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a

reference signal.

6.5

Power Supply Decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors

are not shown in the application circuit. The placement and the size of the decoupling capacitors are very

important to achieve the optimum performance. The CC113LEM reference designs SWRR081 and

SWRR082 should be followed closely.

6.6

PCB Layout Recommendations

The top layer should be used for signal routing, and the open areas should be filled with metallization

connected to ground using several vias.

The area under the chip is used for grounding and shall be connected to the bottom ground plane with

several vias for good thermal performance and sufficiently low inductance to ground.

In the CC113LEM reference designs, SWRR081 and SWRR082, 5 vias are placed inside the exposed die

attached pad. These vias should be “tented” (covered with solder mask) on the component side of the

PCB to avoid migration of solder through the vias during the solder reflow process.

The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process,

which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste

coverage below 100%. See Figure 6-4 for top solder resist and top paste masks.

Applications, Implementation, and Layout

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