CC113LRGPR datasheet(45/87 Pages) TI2

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CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

5.18 General Purpose and Test Output Control Pins

The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with

IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG respectively. Table 5-15 shows

the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the

MCU.

GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will

only be valid when CSn is high. The default value for GDO1 is 3-stated which is useful when the SPI

interface is shared with other devices.

The default value for GDO0 is a 135 - 141 kHz clock output (XOSC frequency divided by 192). Since the

XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal.

When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG.

If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and

GDO2 pins will be hardwired to 0 (1), and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state.

These signals will be hardwired until the CHIP_RDYn signal goes low.

If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins will work as programmed also in

SLEEP state. As an example, GDO1 is high impedance in all states if IOCFG1.GDO1_CFG=0x2E.

Table 5-15. GDOx Signal Selection (x = 0, 1, or 2)

GDOx_CFG[5:0]

Description(1)

Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. Deasserts when RX

0 (0x00)

FIFO is drained below the same threshold.

Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is

1 (0x01)

reached. Deasserts when the RX FIFO is empty.

2 (0x02) –

Reserved - used for test.

3 (0x03)

4 (0x04)

Asserts when the RX FIFO has overflowed. Deasserts when the FIFO has been flushed.

5 (0x05)

Reserved - used for test.

Asserts when sync word has been received, and de-asserts at the end of the packet. The pin will also de-assert when

6 (0x06)

a packet is discarded due to address or maximum length filtering or when the radio enters RXFIFO_OVERFLOW

state.

7 (0x07)

Asserts when a packet has been received with CRC OK. Deasserts when the first byte is read from the RX FIFO.

8 (0x08)

Reserved - used for test.

9 (0x09)

Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting).

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high.

10 (0x0A)

To check for PLL lock the lock detector output should be used as an interrupt for the MCU.

Serial Clock. Synchronous to the data in synchronous serial mode. Data is set up on the falling edge by CC113L when

11 (0x0B)

GDOx_INV=0.

12 (0x0C)

Serial Synchronous Data Output. Used for synchronous serial mode.

13 (0x0D)

Serial Data Output. Used for asynchronous serial mode.

14 (0x0E)

Carrier sense. High if RSSI level is above threshold. Cleared when entering IDLE mode.

15 (0x0F)

CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.

16 (0x10) –

Reserved - used for test.

27 (0x1B)

LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA in

28 (0x1C)

applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.

29 (0x1D) –

Reserved - used for test.

38 (0x26)

39 (0x27)

CLK_32k.

40 (0x28)

Reserved - used for test.

(1)

There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one

of the GDO pins, the other two GDO pins must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.

To optimize RF performance, these signals should not be used while the radio is in RX.

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