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CC113LRGPR датащи(PDF) 60 Page - Texas Instruments |
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CC113LRGPR датащи(HTML) 60 Page - Texas Instruments |
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60 / 87 page ![]() CC113L SWRS108B – MAY 2011 – REVISED JUNE 2014 www.ti.com Table 5-44. 0x18: MCSM0 - Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:6 R0 Not used Automatically calibrate when going to or from RX mode Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe) 1 (01) When going from IDLE to RX 5:4 FS_AUTOCAL[1:0] 0 (00) R/W When going from RX back to IDLE 2 (10) automatically Every 4th time when going from RX to IDLE 3 (11) automatically Programs the number of times the six-bit ripple counter must expire after the XOSC has settled before CHP_RDYn goes low.(1) If XOSC is on (stable) during power-down, PO_TIMEOUT shall be set so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low (PO_TIMEOUT=2 recommended). Typical start-up time for the voltage regulator is 50 μs. For robust operation it is recommended to use PO_TIMEOUT = 2 or 3 when XOSC is off during power-down. Timeout after Setting Expire count 3:2 PO_TIMEOUT 1 (01) R/W XOSC start Approximately 2.3 0 (00) 1 - 2.4 μs Approximately 37 - 1 (01) 16 39 μs Approximately 149 2 (10) 64 - 155 μs Approximately 597 3 (11) 256 - 620 μs Exact timeout depends on crystal frequency. 1 0 R/W Use setting from SmartRF Studio SWRC176 0 XOSC_FORCE_ON 0 R/W Force the XOSC to stay on in the SLEEP state. (1) Note that the XOSC_STABLE signal will be asserted at the same time as the CHIP_RDYn signal; that is, the PO_TIMEOUT delays both signals and does not insert a delay between the signals. Table 5-45. 0x19: FOCCFG - Frequency Offset Compensation Configuration Bit Field Name Reset R/W Description 7:6 R0 Not used If set, the demodulator freezes the frequency offset 5 FOC_BS_CS_GATE 1 R/W compensation and clock recovery feedback loops until the CS signal goes high. The frequency compensation loop gain to be used before a sync word is detected. Setting Freq. compensation loop gain before sync word 0 (00) K 4:3 FOC_PRE_K[1:0] 2 (10) R/W 1 (01) 2K 2 (10) 3K 3 (11) 4K The frequency compensation loop gain to be used after a sync word is detected. Setting Freq. compensation loop gain after sync word 2 FOC_POST_K 1 R/W 0 Same as FOC_PRE_K 1 K/2 60 Detailed Description Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC113L |
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