CC113LRGPR datasheet(21/87 Pages) TI2

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Header

SRES

Header

Addr

Data

CSn

CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

5.5.2

The configuration registers on the CC113L are located on SPI addresses from 0x00 to 0x2E. Table 5-17

lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate

optimum register settings. The detailed description of each register is found in Section 5.21.1 and

Section 5.21.2. All configuration registers can be both written to and read. The R/W bit controls if the

time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte

is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in

the header byte. The address bits (A5 – A0) set the start address in an internal address counter. This

counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or

a write access and must be terminated by setting CSn high.

For register addresses in the range 0x30 – 0x3D, the burst bit is used to select between status registers

when burst bit is one, and command strobes when burst bit is zero (see Section 5.5.3). Because of this,

burst access is not available for status registers and they must be accessed one at a time. The status

registers can only be read.

5.5.3

SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio

hardware (that is, MARCSTATE or RXBYTES), there is a small, but finite, probability that a single read

from the register is being corrupt. As an example, the probability of any single read from RXBYTES being

corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC113L Errata

Notes SWRZ038 for more details.

5.5.4

Command Strobes

Command Strobes may be viewed as single byte instructions to CC113L. By addressing a command

strobe register, internal sequences will be started. These commands are used to disable the crystal

oscillator, enable receive mode, enable calibration etc. The 8 command strobes are listed in Table 5-16.

NOTE

An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This

means that if for example an SIDLE strobe is issued while the radio is in RX state, any other

command strobes issued before the radio reaches IDLE state will be ignored.

The command strobe registers are accessed by transferring a single header byte (no data is being

transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range

0x30 through 0x3D) are written. The R/W bit can be either one or zero and will determine how the

FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an

SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can

be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of

the SPWD and the SXOFF strobes, which are executed when CSn goes high.

Figure 5-4. SRES Command Strobe

Detailed Description

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