CC113LRGPR datasheet(49/87 Pages) TI2

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CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

5.21 Configuration Registers

The configuration of CC113L is done by programming 8-bit registers. The optimum configuration data

based on selected system parameters are most easily found by using the SmartRF Studio software

SWRC176. Complete descriptions of the registers are given in the following tables. After chip reset, all the

registers have default values as shown in the tables. The optimum register setting might differ from the

default value. After a reset, all registers that shall be different from the default value therefore needs to be

programmed through the SPI interface.

There are 8 command strobe registers, listed in Table 5-16. Accessing these registers will initiate the

change of an internal state or mode. There are 43 normal 8-bit configuration registers listed in Table 5-17

and SmartRF Studio will provide recommended settings for these registers (Addresses marked as “Not

Used” can be part of a burst access and one can write a dummy value to them. Addresses marked as

“Reserved” must be configured according to SmartRF Studio ).

There are also 8 status registers that are listed in Table 5-18. These registers, which are read-only,

contain information about the status of CC113L.

The RX FIFO is accessed through one 8-bit register. During the header byte transfer and while writing

data to a register, a status byte is returned on the SO line. This status byte is described in Table 5-2

Table 5-19 summarizes the SPI address space. The address to use is given by adding the base address

to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for

base addresses above and below 0x2F.

Table 5-16. Command Strobes

Address

Strobe Name

Description

0x30

SRES

Reset chip.

0x31

Reserved

0x32

SXOFF

Turn off crystal oscillator.

Calibrate frequency synthesizer and turn it off. SCAL can be strobed

0x33

SCAL

from IDLE mode without setting manual calibration mode (

MCSM0.FS_AUTOCAL=0)

In IDLE state: Enable RX. Perform calibration first if

0x34

SRX

MCSM0.FS_AUTOCAL=1.

0x35

Reserved

0x36

SIDLE

Enter IDLE state

0x37 - 0x38

Reserved

0x39

SPWD

Enter power down mode when CSn goes high.

Flush the RX FIFO buffer. Only issue SFRX in IDLE or

0x3A

SFRX

RXFIFO_OVERFLOW states.

0x3B - 0x3C

Reserved

0x3D

SNOP

No operation. May be used to get access to the chip status byte.

Detailed Description

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