TUSB1146 datasheet(10/68 Pages) TI2

10 / 68 page

TUSB1146

SLLSFB2 – APRIL 2020

www.ti.com

Product Folder Links: TUSB1146

Submit Documentation Feedback

USB and DP Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CPHF-LINRL0

High-frequency 1-dB compression

point at LINR_L0 setting.

At 5 GHz, 200 mVpp < VID < 1200

mVpp

550

mVpp

CPLF-LINRL1

Low-frequency 1-dB compression

point at LINR_L1 setting.

At 100 MHz, 200 mVpp < VID < 1200

mVpp

700

mVpp

CPHF-LINRL1

High-frequency 1-dB compression

point at LINR_L1 setting.

At 5 GHz, 200 mVpp < VID < 1200

mVpp

650

mVpp

CPLF-LINRL2

Low-frequency 1-dB compression

point at LINR_L2 setting.

At 100 MHz, 200 mVpp < VID < 1200

mVpp

800

mVpp

CPHF-LINRL2

High-frequency 1-dB compression

point at LINR_L2 setting.

At 5 GHz, 200 mVpp < VID < 1200

mVpp

750

mVpp

CPLF-LINRL3

Low-frequency 1-dB compression

point at LINR_L3 setting.

At 100 MHz, 200 mVpp < VID < 1200

mVpp

900

mVpp

CPHF-LINRL3

High-frequency 1-dB compression

point at LINR_L3 setting.

At 5 GHz, 200 mVpp < VID < 1200

mVpp

830

mVpp

fLF

Low frequency cutoff

200 mVPP< VID < 1200 mVPP

kHz

tTX_DJ_USB

TX output deterministic residual jitter

when operating in USB mode.

Optimual EQ setting; 12-in prechannel

(SDD21 = -11.2dB); 1.6-in post

channel (SDD21 = -1.8dB); PRBS7;

10 Gbps

.07

tTX_DJ_DP

TX output deterministic residual jitter

when operating in DP mode.

Optimual EQ setting;12-in prechannel

(SDD21 = -11.2dB); 1.6-in post

channel (SDD21 = -1.8dB); PRBS7;

8.1 Gbps

.04

DisplayPort Receiver (DP[3:0]p/n)

VID(PP)

Peak-to-peak input differential

dynamic voltage range

1400

VIC

Input common mode voltage

1.75

VRX_CM-INST

Max Instantaneous RX DC common

mode voltage change under all

operating conditions (OFF to ON,

Disabled to 4DP, etc…)

Measured single-ended at non-

TUSB1146 side of AC coupling

capacitor with 50-

Ω load.

-300

500

Data rate

Gbps

R(ti)

Input termination resistance

110

C(AC)

External required AC coupling

capacitance

265

EQ_DP15

DP0 Receiver equalization at 4.05

GHz

FLIPSEL = 0; DP0EQ_SEL = 15;

EQ_DP15

DP0 Receiver equalization at 5 GHz

FLIPSEL = 0; DP0EQ_SEL = 15;

12.3

DisplayPort Transmitter (TX1p/n, TX2p/n, RX1p/n, RX2p/n)

VTX-CM-INST

Max Instantaneous TX DC common

mode voltage change under all

operating conditions (Disabled to 4DP,

etc…)

Measured at non-TUSB1146 side of

AC coupling capacitor with 50-

Ω load.

-500

1000

VTX(DC-CM)

Common-mode voltage bias in the transmitter (DC)

AUXp or AUXn and SBU1 or SBU2

RON

Output ON resistance

VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;

VI = 2.7 V to 3.6 V for AUXn

5.5

ΔRON

ON resistance mismatch within pair

VCC = 3.3 V; VI = 0 to 0.4 V for AUXP;

VI = 2.7 V to 3.6 V for AUXN

2.5

RON(FLAT)

ON resistance flatness (RON max –

RON min) measured at identical VCC

and temperature

VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;

VI = 2.7 V to 3.6 V for AUXn

V(AUXP_DC_CM)

AUX Channel DC common mode

voltage for AUXp and SBU1.

VCC = 3.3 V;

0.4

V(AUXN_DC_CM)

AUX Channel DC common mode

voltage for AUXn and SBU2

VCC = 3.3 V;

2.7

3.6

C(AUX_ON)

ON-state capacitance

VCC = 3.3 V; CTL1 = 1; VI = 0 V

or 3.3 V

C(AUX_OFF)

OFF-state capacitance

VCC = 3.3 V; CTL1 = 0; VI = 0 V

or 3.3 V

TUSB1146 датащи(PDF) 10 Page - Texas Instruments

TUSB1146 датащи(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL