TUSB1146 datasheet(4/68 Pages) TI2

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TUSB1146

SLLSFB2 – APRIL 2020

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TUSB1146 Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

(1)

Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.

RX2p

Diff I/O

Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing

port.

RX2n

Diff I/O

Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream

Facing port.

SSTXp

Diff I

Differential positive input for USB3.1 upstream facing port.

SSTXn

Diff I

Differential negative input for USB3.1 upstream facing port.

SSRXp

Diff O

Differential positive output for USB3.1 upstream facing port.

SSRXn

Diff O

Differential negative output for USB3.1 upstream facing port.

EQ1

4 Level I

This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2

when USB used. Refer to Table 7 for details on the equalization setting.

EQ0

4 Level I

This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2

when USB used. Refer to Table 7 for details on the equalization setting.

CAD_SNK/DCI_DAT(1)

I/O

(PD)

When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used. When I2C_EN =

0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).

HPDIN/DCI_CLK(1)

I/O

(PD)

When I2C_EN ! = 0, this pin functions as DCI clock output Leave open if not used. When I2C_EN =

0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for

greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed.

I2C_EN

4 Level I

I2C Programming Mode or GPIO Programming Select.

0 = GPIO mode (I2C disabled) with adaptive EQ disabled.

R = TI Test Mode (I2C enabled at 3.3 V)

F = I2C enabled at 1.8 V when EQ0 = "0" and EQ1 = "0". All other combinations of EQ0 and EQ1 are

reserved.

1 = I2C enabled at 3.3 V.

SBU1

I/O, CMOS

SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm resistor

to GND is also recommended.

SBU2

I/O, CMOS

SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm resistor

to GND is also recommended.

AUXp

I/O, CMOS

AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This pin

along with AUXN is used by the TUSB1146 for AUX snooping and is routed to SBU1/2 based on the

orientation of the Type-C.

AUXn

I/O, CMOS

AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to VCC (3.3V).

This pin along with AUXP is used by the TUSB1146 for AUX snooping and is routed to SBU1/2

based on the orientation of the Type-C.

DPEQ1

4 Level I

DisplayPort Receiver EQ. Along with DPEQ0, this pin selects the DisplayPort receiver equalization

gain. Refer to Table 9 for details on the equalization settings.

DPEQ0/A1

4 Level I

DisplayPort Receiver EQ. Along with DPEQ1, this pin selects the DisplayPort receiver equalization

gain. When I2C_EN is not ‘0’, this pin will also set the TUSB1146 I2C address. Refer to Table 9 for

details on the equalization settings.

SSEQ1

4 Level I

Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N. Refer to

Table 8 for details on the equalization settings.

SSEQ0/A0

4 Level I

Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When

I2C_EN is not ‘0’, this pin will also set the TUSB1146 I2C address. Refer to Table 8 for details on the

equalization settings.

FLIP/SCL

2 Level I

When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock

pull-up to I2C master's VCC I2C supply.

CTL0/SDA

2 Level I

When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for

I2C data pullup to I2C master's VCC I2C supply.

CTL1/HPDIN

2 Level I

(Failsafe)

(PD)

DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort

functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled

through I2C registers.

L = DisplayPort Disabled.

H = DisplayPort Enabled.

When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink. When

this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU switch

will remain closed.

VCC

1, 6, 20, 28

3.3-V Power Supply

Thermal Pad

Ground

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