TUSB1146 datasheet(36/68 Pages) TI2

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Slave Address

Write

Ack

Start

Repeated Start

Slave Address

Data from Register Xh

Read

Stop

Data from Register Xh + 1

Slave Address

Data from offset 0x00

last read address + 1

Read

Ack

Start

Stop

TUSB1146

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4. The TUSB1146 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I2C register.

6. The TUSB1146 acknowledges the byte transfer

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TUSB1146.

8. The master terminates the write operation by generating a stop condition (P).

Figure 30. I2C Read without repeated Start

The following procedure should be followed to read the TUSB1146 I2C registers without a repeated Start (refer

Figure 30).

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit

address and a zero-value “W/R” bit to indicate a read cycle.

2. The TUSB1146 acknowledges the 7-bit address cycle.

3. Following the acknowledge the master continues sending clock.

4. The TUSB1146 transmit the contents of the memory registers MSB-first starting at register 00h or last read

5. The TUSB1146 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after

each byte transfer; the I2C master acknowledges reception of each data byte transfer.

6. If an ACK is received, the TUSB1146 transmits the next byte of data as long as master provides the clock. If

a NAK is received, the TUSB1146 stops providing data and waits for a stop condition (P).

7. The master terminates the write operation by generating a stop condition (P).

Figure 31. I2C Read with repeated Start

The following procedure should be followed to read the TUSB1146 I2C registers with a repeated Start (refer

Figure 31).

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB1146 acknowledges the 7-bit address cycle.

3. The master presents the register offset within TUSB1146 to be written, consisting of one byte of data, MSB-

first.

4. The TUSB1146 acknowledges the register offset cycle.

5. The master presents a repeated start condition (Sr).

6. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit

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