TMP512 datasheet(24/62 Pages) TI2

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TMP512

TMP513

SBOS491A

– JUNE 2010 – REVISED MAY 2011

www.ti.com

In applications that do not have large energy storage

not generate an Acknowledge and continues to hold

electrolytics on one or both sides of the shunt, an

the ALERT line low until the interrupt is cleared.

input

overstress

condition

may

result

from

Successful completion of the read alert response

excessive dV/dt of the voltage applied to the input. A

protocol clears the SMBus ALERT pin, provided that

hard physical short is the most likely cause of this

the condition causing the alert no longer exists. The

event, particularly in applications with no large

SMBus Alert flag is cleared separately by either

electrolytics present. This problem occurs because an

reading the Status Register or by disabling the

excessive dV/dt can activate the ESD protection in

SMBus Alert function.

the TMP512/13 in systems where large currents are

The Status Register flags indicate which (if any) of

available. Testing has demonstrated that the addition

the watchdogs have been activated. After power-on

of 10

Ω resistors in series with each input of the

reset (POR), the normal state of all flag bits is '0',

TMP512/13 sufficiently protects the inputs against

assuming that no alarm conditions exist.

dV/dt failure up to the 26V rating of the TMP512/13.

These

resistors

have

significant

effect

EXTERNAL CIRCUITRY FOR ADDITIONAL

accuracy.

VBUS INPUT

SMBus ALERT RESPONSE

The TMP512/13 GPIO can be used to control an

external circuit to switch the VBUS measurement to an

The SMBus alert response functions only when the

alternate location. Switching is most often done to

Alert pin is active and in latch mode (03h, bit 0 = 1);

perform bus voltage measurements on the opposite

see Figure 26. The ALERT interrupt output signal is

side of a MOSFET switch in series with the shunt

latched and can be cleared only by either reading the

resistor.

Status Register or by successfully responding to an

alert response address. If the fault is still present, the

Consideration must be given to the typical 20

μA input

ALERT pin re-asserts. Asserting the ALERT pin does

current of each TMP512/13 input, along with the

not halt automatic conversions that are already in

320k

Ω impedance present at the VIN– input where the

progress. The ALERT output pin is open-drain,

bus voltage is measured. These effects can create

allowing multiple devices to share a common interrupt

errors

through

the

resistance

any

external

line.

switching method used. The easiest way to avoid

these errors is by reducing this resistance to a

The

TMP512/13

respond

the

SMBus

alert

minimum; select switching MOSFETs with the lowest

response address, an interrupt pointer return-address

possible RDS(on) values.

feature. The SMBus alert response interrupt pointer

provides quick fault identification for simple slave

The circuit shown in Figure 31 uses MOSFET pairs to

devices. When an ALERT occurs, the master can

reduce package count. Back-to-back MOSFETs must

broadcast the alert response slave address (0001

be used in each leg because of the built-in back

100). Following this alert response, any slave devices

diodes from source-to-drain. In this circuit, the normal

that generated interrupts identify themselves by

connection for VIN– is at the shunt, with the optional

putting the respective addresses on the bus.

voltage measurement at the output of the control

FET.

The alert response can activate several different

slave devices simultaneously, similar to the two-wire

General Call. If more than one slave attempts to

respond, bus arbitration rules apply; the device with

the lower address code wins. The losing device does

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