L99MH98 datasheet(63/147 Pages) STMICROELECTRONICS

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VDS

monitoring

HS8

VDS

monitoring

HS7

VDS

monitoring

HS6

VDS

monitoring

HS5

VDS

monitoring

HS4

VDS

monitoring

HS3

VDS

monitoring

HS2

CP LOW

flag

Table 46. DSR2 (0x03) LSB description

Bit

Name

Description

VDSLS7

VDS monitoring flags

Flag VDSLSx (x = 1...8) is set and latched as soon as the VDS of the corresponding LS MOSFET exceeds the

relative threshold (set by VDS_CONFx, x = 1...8) for a time longer than the corresponding filtering time or

blanking filtering time, where the blanking time is applicable. It can be cleared by SPI only if the source of the

fault is no longer present

VDSLS6

VDSLS5

VDSLS4

VDSLS3

VDSLS2

VDSLS1

CPLOW

CP low flag

If the CP_LOW_CONFIG control bit is set to one, the CPLOW status flag becomes a status bit (set and reset

automatically) and the gate drivers come out of forced disabled mode automatically upon recovery from the

charge pump low voltage condition. In this case the status bit will be automatically cleared as soon as the

charge pump output voltage is no longer below the low voltage threshold for a time longer than tCP

If the CP_LOW_CONFIG control bit is set to zero, the gate drivers come out of forced disabled mode only once

the charge pump low-voltage flag CPLOW is cleared via SPI. The charge pump low voltage flag CPLOW can

be cleared by a SPI “read and clear” command only if the charge pump low-voltage condition is no longer

present, namely if VCP > VCP_LOW for a time longer than tCP

L99MH98

SPI Registers

DS14611 - Rev 3

page 63/147

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