L99MH98 datasheet(54/147 Pages) STMICROELECTRONICS

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6.4.5

Access after RESET scenario

•

Frame n

–

SDI:

◦

Bit 23 = 0 or 1 (read or write command on the OpCode)

◦

Bit 22 = Not used

◦

Bits 21 to 16 = Address of the register to read or write

◦

Bits 15 to 1 = Data to write (if write command was chosen) or all ‘0’ (if read command was

chosen)

◦

Bit 0 = Parity bit

–

SDO:

◦

Bit 23 = 0 (no SPI error or RESET in the previous access)

◦

Bit 22 = GSBN bit (1 = No fault)

◦

Bits 21 to 16 = Address of the register selected in the previous frame (n-1)

◦

Bits 15 to 1 = Data value of the register selected in the previous frame (n-1)

◦

Bit 0 = Parity bit

•

Frame n+1

–

SDI:

◦

Bit 23 = 0 or 1 (read or write command on the OpCode)

◦

Bit 22 = Not used

◦

Bits 21 to 16 = Address of the register to read or write

◦

Bits 15 to 1 = Data to write into the chosen register

◦

Bit 0 = Parity bit

–

SDO:

◦

Bit 23 = 1 (SPI error or RESET event in the previous access)

◦

Bit 22 = GSBN bit (1 = No fault)

◦

Bits 21 to 16 = Address of the STATUS register

◦

Bits 15 to 1 = Data value of the STATUS register

◦

Bit 0 = Parity bit

Figure 37. Access after RESET scenario

Frame n

Read or

Write cmd

Address of the register

to read reg1

Status register bit15, bit14 and bit1 are set to ‘0’  no fault, no reset

Frame n+1

Data field

Reset event between

the two frames SPI

As soon the reset event happens the status register

value is updated with bit15 set to ‘1’

Data value of STATUS register (saved at frame n+1

cs falling) independently of which register has been

selected by SDI during previous frame (n)

SPI Error or RESET

1 means: or SPI error in previous access

(frame n-1) or reset before this access

L99MH98

Serial peripheral interface (SPI)

DS14611 - Rev 3

page 54/147

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