L99MH98 datasheet(48/147 Pages) STMICROELECTRONICS

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6.3.1.1

OpCode

The operating code is used to distinguish between different commands/operations on registers of the receiver

device.

Table 32. OpCode

MSB

Description

Read command

Write command

A Write command (with no parity error, no wrong address and no CLK count error) will modify the content of the

addressed control register with the payload at the next communication start. Besides this a shift out of the content

(data present at communication start) of the addressed register is performed.

With the Read command two different events can be performed

•

A Read event shifts out in the frame n+1 the data’s addressed in the frame n. In this case all the bits of the

payload data sent in the frame n is set to 0, and the data of the addressed register will not be modified.

•

A Clear on Read event shifts out in the frame n+1 the data’s addressed in the frame n, but with some bits

that are cleared. In this case all the bits of the payload data sent that must be cleared will be set to 1, the

bits that must not be cleared will be put to 0.

6.3.1.2

Address

The Address bits are used to indicate the register on which the command/operation will be performed:

•

In case of read command (frame n) on the OpCode bit, the Address bits indicate the register you want to

read. The contents of the register to be read will be put in the next frame (n+1) sent by the SDO pin.

•

In case of write command on the OpCode bit, the Address bits indicate the register where the data bytes

must be written.

6.3.1.3

Data word

The payload (Data Byte 2 to Data Byte 1) is the data transferred to the device with every SPI communication. The

payload always follows the Address bits.

•

For a Write access the payload represents the new data written to the addressed register.

•

For a Read operation the payload is not used. The payload will be all set to ‘0’.

•

For a Clear on Read operation the payload is used. All the bits that must be cleared will be set to ‘1’, all the

others will be set to ‘0’.

6.3.1.4

Parity bit

A parity bit is a bit added at the end of the 24 bits of each frame as an error detection code.

An odd parity bit for each communication must be calculated considering the entire 24-bit frame. The frame is

considered valid only if the result of the Parity check is valid, which means an odd number of ‘1’ is present in the

SDI frame, if not the frame will be ignored and an SPI_ERROR event will be triggered.

6.3.2

SDO frame

The Data-Out frame consists of 24 bits (SPI ERROR (1 bit) + GSBN (1 bit) + Address (6 bits) + Data Byte 2 (8

bits) + Data Byte 1 (7 bits) + Parity bit (1 bit)).

•

SPI ERROR = The first transmitted bit (MSB) contains the information about a SPI error or RESET

•

GSBN = Global Status bit, used only in the SDO frame (MSB-1)

•

Address = The following 6 bits (MSB-2 to MSB-7) represent the register address on which the command/

operation will be performed

•

Data Bytes = The subsequent 15 bits (MSB-8 to MSB-22) contain the payload

•

Parity bit = Last bit (MSB-23) contains the parity bit for the integrity check

6.3.2.1

SPI ERROR bit

The SPI ERROR bit contains the information about a SPI error or a RESET event according to the Table 33:

L99MH98

Serial peripheral interface (SPI)

DS14611 - Rev 3

page 48/147

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