STM32WL33C8 datasheet(28/91 Pages) STMICROELECTRONICS

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Supported I2S protocols:

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I2S Philips standard

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MSB-Justified standard (left-justified)

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LSB-Justified standard (right-justified)

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PCM standard (with short and long frame synchronization on 16-bit channel frame or 16-bit data

frame extended to 32-bit channel frame)

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Data direction is always MSB first

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DMA capability for transmission and reception (16-bit wide)

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Master clock can be output to drive an external audio component. Ratio is fixed at 256 × FS (where FS is

the audio sampling frequency)

3.23

Liquid crystal display controller (LCD)

The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8

common terminals and up to 16 segment terminals to drive 64 (16x4) or 96 (12x8) LCD picture elements (pixels).

The exact number of terminals depends on the device pinout.

The LCD is made up of several segments (pixels or complete symbols) which can be turned visible or invisible.

Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage

greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The segment

voltage must be alternated to avoid an electrophoresis effect in the liquid crystal (which degrades the display).

The waveform across a segment must then be generated so as to avoid having a direct current (DC).

The main LCD features are:

•

Highly flexible frame rate control.

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Supports Static, 1/2, 1/3, 1/4 and 1/8 duty

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Supports Static, 1/2, 1/3 and 1/4 bias

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Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application

firmware without affecting the integrity of the data displayed.

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LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)

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Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax

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No need for external analog components:

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Astep-up converter is embedded to generate an internal VLCD voltage higher than VDD

–

Software selection between external and internal VLCD voltage source. In the case of an external

source, the internal boost circuit is disabled to reduce power consumption

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A resistive network is embedded to generate intermediate VLCD voltages

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The structure of the resistive network is configurable by software to adapt the power consumption to

match the capacitive charge required by the LCD panel.

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Integrated voltage output buffers for higher LCD driving capability

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The contrast can be adjusted using two different methods:

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When using the internal step-up converter, the software can adjust VLCD between VLCDmin and

VLCDmax

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Programmable dead time (up to 8 phase periods) between frames

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Full support of Low power modes: the LCD controller can be displayed in DEESTOP mode or can be fully

disabled to reduce power consumption

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Built in phase inversion for reduced power consumption and EMI (electromagnetic interference)

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Start of frame interrupt to synchronize the software when updating the LCD data RAM

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Blink capability:

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Up to 1, 2, 3, 4, 8 or all pixels which can be programmed to blink at a configurable frequency

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Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz

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Used LCD segment and common pins should be configured as GPIO alternate functions and unused

segment, and common pins can be used for general purpose I/O or for another peripheral alternate

function.

STM32WL33xx

Functional overview

DS14221 - Rev 5

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