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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32WL33C8 датащи(PDF) 7 Page - STMicroelectronics |
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STM32WL33C8 датащи(HTML) 7 Page - STMicroelectronics |
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7 / 91 page  3 Functional overview 3.1 Architecture The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller subsystem using an Arm Cortex-M0+ core. The main system consists of a 32-bit multilayer AHB bus-matrix interconnect: • Three masters: – CPU (Cortex® -M0+) core S-bus – DMA1 – Sub-1 GHz radio subsystem • Seven slaves: – Internal flash memory on CPU (Cortex®-M0+) S bus – Internal SRAM0 (16 Kbytes) – Internal SRAM1 (16 Kbytes) – APB0 peripherals (through an AHB to APB bridge) – APB1 peripherals (through an AHB to APB bridge) – AHB0 peripherals – AHBRF including AHB to APB bridge and Radio peripherals (connected to APB2) The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 2. Figure 2. STM32WL33xx system architecture BusMatrix 6x7 BusMatrix 6x7 AHB0 peripherals ARM Cortex-M0+ SRAM1 APB0 peripherals Flash APB2 LPAWUR Flash Controller APB1 peripherals DMA 7ch S0 S1 SRAM0 Radio system S3 S4 S5 S2 AHB2APB AHB2APB AHB2APB AHB UP Conv seq AHB DOWN conv STM32WL33xx Functional overview DS14221 - Rev 5 page 7/91 |
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