STM32WL33C8 datasheet(8/91 Pages) STMICROELECTRONICS

номер детали	STM32WL33C8

подробное описание детали	Multiprotocol LPWAN 32-bit MCU Arm® Cortex®-M0 2(G)FSK, 4(G)FSK, ASK, D-BPSK, up to 256KB flash, 32KB SRAM

PDF	91 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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The system consists of a Cortex®-M0+ “Radio protocol and application” processor with its radio sub-system.

There is a single flash memory to be used by the CPU for both sub-1 GHz protocols and application

management. The peripherals are located on the different system buses (AHB, APB0, APB1, APB2 for the radio

system). There are 2 SRAM banks, a SRAM0 always power supplied and SRAM1 that can be programmed to be

always on or switchable.

3.2

Arm Cortex-M0+ core with MPU

The STM32WL33xx contains an Arm Cortex-M0+ microcontroller core. The Cortex-M0+ provides a low-cost

platform that meets the needs of CPU implementation, with a reduced pin count and low-power consumption,

while delivering outstanding computational performance and an advanced response to interrupts. The Cortex-M0+

can run from 1 MHz up to 64 MHz. The Cortex-M0+ processor is built on a highly area and power optimized 32-bit

processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy

efficiency through a small but powerful instruction set and extensively optimized design, providing high-end

processing hardware including a single-cycle multiplier. The interrupts are handled by the Cortex-M0+ nested

vector interrupt controller (NVIC). The NVIC controls specific Cortex-M0+ interrupts as well as the STM32WL33xx

peripheral interrupts. With its embedded Arm core, the STM32WL33xx family is compatible with all Arm tools and

software.

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 8/91

STM32WL33C8 датащи(PDF) 8 Page - STMicroelectronics