STM32WL33C8 datasheet(9/91 Pages) STMICROELECTRONICS

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3.3

Memories

3.3.1

Embedded flash memory

The flash controller implements the erase and program flash memory operation. The flash controller also

implements the read and write protection.

The flash memory features are:

•

Memory organization:

–

1 bank of 256 Kbytes

–

Page size: 2 Kbytes

•

32-bit wide data read/write

•

Page erase (2 Kbytes) and mass erase

Flash controller features:

•

flash memory read operations

•

flash memory write operations: single data write, or 4x32-bits burst write

•

flash memory erase operations

•

page write protection mechanism (by 4 segments of variable sizes from 1 to 127 pages)

Option-byte loader hardware mechanism reserved for ST analog trimming bits.

3.3.2

Embedded SRAM

The STM32WL33xx integrates a total of 32 Kbytes of embedded SRAM split into two 16 Kbyte banks.

3.3.3

Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbyte dedicated for user data. The user can protect the

OTP data area by writing the last word at address 0x1000 1BFC and by performing a system reset. This operation

freezes the OTP memory from further unwanted write operations.

3.3.4

Memory protection unit (MPU)

The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or

resources used by any other active task. This memory area is organized into up to 8 protected areas. The MPU is

especially helpful for applications where critical or certified code must be protected against the behavior of other

tasks.

3.4

RF subsystem

The STM32WL33xx embeds an ultra-low-power radio supporting Sub-1GHz operation.

It integrates a high performance ultra-low power Sub-1GHz transceiver supporting different modulation schemes:

2(G)FSK, 4(G)FSK, OOK and ASK and air data rate programmable from 0.1 to 300 kbit/s for 2-GFSK and up to

600 kbit/s for 4-GFSK.

Moreover, the device integrates a Wake-Up radio system based on OOK receiver (LPAWUR).

The STM32WL33xx RF output power can be programmed to deliver up to +20 dBm, in TX+TXHP mode, enabling

long communication ranges. Up to +16 dBm in TXHP mode or up to +10 dBm in TX modes, exploiting the

extremely optimized architecture for ultra-low-current consumption and battery-operated system.

The STM32WL33xx receiver offers best in class sensitivity performance together with extremely low current

consumption. Moreover, it is compliant with ETSI CAT1 adjacent channel selectivity specification and very high

blocker rejection, resulting in receiver robustness and in the capability to demodulate packets even in the

presence of high interferer signals in very crowed frequency channel.

The IQ data access in receiver mode, coupled with polar mode control of the transmitter, enables the

implementation of custom modulation schemes using the embedded microcontroller or using an external DSP.

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 9/91

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