ADS9217 datasheet(11/68 Pages) TI2

11 / 68 page

6.7 Switching Characteristics

at AVDD_5V = 4.75V to 5.25V, VDD_1V8 = 1.75V to 1.85V, internal VREF = 4.096V, and maximum throughput (unless

otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RESET

tPU

Power-up time for device

LVDS DATA INTERFACE

tRT

Rise time

With 50Ω

transmission line of

length = 20mm,

differential RL =

100Ω, and CL = 1pF

600

tFT

Fall time

600

tCYCLE

Sampling clock period

ADS9119

ADS9118

100

ADS9117

200

tDCLK

Clock output

4.167

Clock duty cycle

td_DCLKDO

Time delay: DCLKP rising to corresponding

data valid

SDR mode

–0.35

0.35

toff_DCLKDO_r

Time offset: DCLKP rising to corresponding

data valid

DDR mode

tDCLK / 4 – 0.35

tDCLK / 4 + 0.35

toff_DCLKDO_f

Time offset: DCLKP falling to corresponding

data valid

DDR mode

tDCLK / 4 – 0.35

tDCLK / 4 + 0.35

tPD

Time delay: SMPL_CLK falling to DCLKP

rising

tDCLK

tPU_SMPL_CLK

Time delay: Free-running clock connected

to SMPL_CLK to ADC data valid

100

µs

tLAT (1)

Time delay: Internal digital delay to MSB of

data output

SPI TIMINGS

tden_CKDO

Time delay: 8th SCLK rising edge to SDO

enable

tdz_CKDO

Time delay: 24th SCLK rising edge to SDO

going Hi-Z

td_CKDO

Time delay: SCLK launch edge to

corresponding data valid on SDO

tht_CKDO

Hold time: SCLK launch edge to previous

data valid on SDO

(1)

See section on ADC Sampling Clock Input for more details on data output latency.

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SLVSIN3 – MAY 2025

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