ADS9217 datasheet(32/68 Pages) TI2

32 / 68 page

N x 24 bits

SCLK

PICO

Logic 0 (when SPI_MODE = 0b)

POCI

DADCN

DADC3

DADC2

DADC1

Figure 7-16. Register Write With Daisy-Chain

N x 24 bits

SCLK

DAISY_CHAIN_LEN = 3 {ADC1}

DAISY_CHAIN_LEN = 0 {ADC2, ADC3, and ADCN}

DADC1[23:0] = DADC2[23:0] = DADC3[23:0] = DADCN[23:0] = { 0000 0001, 0000 0000, N-1, 00}

PICO

Logic 0 (when SPI_MODE = 0b)

POCI

Frame 1

Frame 2

DADCN

DADC3

DADC2

DADC1

DADCN

DADC3

DADC2

DADC1

Frame 3

DADCN

DADC3

DADC2

DADC1

Frame N

DADCN

DADC3

DADC2

DADC1

DAISY_CHAIN_LEN = 3 {ADC1 and ADC2}

DAISY_CHAIN_LEN= 0 {ADC3, ADCN}

DAISY_CHAIN_LEN = 3 {ADC1, ADC2 and ADC3}

DAISY_CHAIN_LEN = 0 {ADCN}

DAISY_CHAIN_LENGTH = 3 {ADC1,

ADC2, ADC3 and ADCN}

Figure 7-17. Register Write to Configure Daisy-Chain Length

7.5.3.2 Register Read With Daisy-Chain

Figure 7-18 illustrates an SPI waveform for reading registers in daisy-chain configuration. Steps for reading

registers from N ADCs connected in a daisy-chain are:

1. Register read is enabled by writing to the following registers:

a. Write to PAGE_SEL to select the desired register bank

b. Enable register reads by writing SPI_RD_EN = 0b (default on power-up)

2. With the register bank selected and SPI_RD_EN = 0b, the controller reads register data by:

a. N × 24-bit SPI frame containing the 8-bit register address to be read: N times (0xFE, 0x00, 8-bit register

address)

b. N × 24-bit SPI frame to read out register data: N times (0xFF, 0xFF, 0xFF)

The 0xFE in step 2a configures the ADC for register read from the specified 8-bit address. At the end of step 2a,

the output shift register in the ADC is loaded with register data. The ADC returns the 8-bit register address and

corresponding 16-bit register data in step 2b.

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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