ADS9217 datasheet(28/68 Pages) TI2

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7.3.9 ADC Sampling Clock Input

Use a low-jitter external clock with a high slew rate to maximize SNR performance. Operate the ADS911x with

a differential or single-ended clock input. Clock amplitude impacts the ADC aperture jitter and, consequently,

SNR. For maximum SNR performance, provide a clock signal with fast slew rates that maximizes swing between

VDD_1V8 and GND levels.

Make sure the sampling clock is a free-running continuous clock. The ADC generates a valid output data, data

clock, and frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics after a free-running sampling

clock is applied. When the sampling clock is stopped, the ADC is in power-down and the output data, data clock,

and frame clock are invalid.

Figure 7-11 shows a diagram of the differential sampling clock input. For this configuration, connect the

differential sampling clock input to the SMPL_CLKP and SMPL_CLKM pins. Figure 7-12 shows a diagram

of the single-ended sampling clock input. In this configuration, connect the single-ended sampling clock to

SMPL_CLKP and connect SMPL_CLKM to ground.

5.4 k

–

Bias

SMPL_CLKP

SMPL_CLKM

Differential

sampling clock

Figure 7-11. AC-Coupled Differential Sampling

Clock

SMPL_CLKP

SMPL_CLKM

GND

VDD_1V8

ADS92XX

Figure 7-12. Single-Ended Sampling Clock

Figure 6-6 shows the latency from analog input sampling instant to corresponding data MSB output marked by

the FCLK rising edge. The equations for data output latency depend on the output data frame width and are

given in Table 7-10.

Table 7-10. Data Output Latency

DEVICE

24-BIT DATA FRAME

20-BIT DATA FRAME

ADS9119

2 × tSMPL_CLK + tLAT

Not supported

ADS9118

1.83 × tSMPL_CLK + tLAT

Not supported

ADS9117

1.83 × tSMPL_CLK + tLAT

2 × tSMPL_CLK + tLAT

1. For tLAT, see the Switching Characteristics table.

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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