ADS9217 datasheet(24/68 Pages) TI2

24 / 68 page

Use a decimation factor of either 2, 4, 8, or 16 with the DDC. Table 7-5 shows the register configuration for

decimating the DDC output.

Table 7-5. Decimation Settings for the DDC

DECIMATION

VALUE

OSR_EN (0x0D[6])

OSR (0x0D[5:2]

OSR_CLK (0xC0[9:7])

Common settings for decimation factors 4, 8,

and 16

CLK3 (0xC5[9])

OSR_INIT1 (0xC0[11:10])

OSR_INIT2 (0xC4[5:4])

OSR_INIT3 (0xC4[1])

OSR_EN (0x0D[6])

OSR (0x0D[5:2]

OSR_CLK (0xC0[9:7])

OSR (0x0D[5:2]

OSR_CLK (0xC0[9:7])

OSR (0x0D[5:2]

OSR_CLK (0xC0[9:7])

7.3.8 Data Interface

The ADS911x features a high-speed, serial LVDS data interface with output data frame width to 20 bits or 24 bits

with the single-data rate (SDR) and double-data rate (DDR) modes.

Configure the INIT_1 register field before writing to other register fields, as described in Table 7-6 and Table 7-7.

Table 7-6. Register Map Settings for Output Data Interface for the ADS9117

DATA

FRAME

WIDTH

(Bits)

DATA

RATE

INIT_1

0x04[3:0]

DATA_LA

NES

0x12[2:0]

DATA_RA

0xC1[8]

CLK1

0xC0[12]

CLK2

0xC1[0]

CLK3

0xC5[9]

CLK4

0xC5[3:2]

CLK5

0xFB[1]

CLK6

0x1C[7:6]

SDR

0x000B

DDR

0x000B

SDR

0x0000

DDR

0x0000

Table 7-7. Register Map Settings for Output Data Interface for the ADS9119 and ADS9118

DATA

FRAME

WIDTH

(Bits)

DATA

RATE

INIT_1

0x04[3:0]

DATA_LA

NES

0x12[2:0]

DATA_RA

0xC1[8]

CLK1

0xC0[12]

CLK2

0xC1[0]

CLK3

0xC5[9]

CLK4

0xC5[3:2]

CLK5

0xFB[1]

CLK6

0x1C[7:6]

SDR

—

Not supported

DDR

—

Not supported

SDR

—

DDR

—

The ADS911x generates a data clock DCLK that is a multiple of the ADC sampling clock SMPL_CLK. The data

clock frequency depends on the data frame width and data rate. The data frame width is 20 or 24 bits and the

data rate is SDR or DDR. The following equation calculates the DCLK speed. Table 7-8 lists the possible values

for the output data clock frequency.

DCLKspeed= DataFrameWidth 24bitor20bit

DataRateSDR=1,DDR=2 ×SMPL_CLK

(4)

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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