VOUT1

VOUT2

VOUT3

VOUT4

VIN

OVP

500 s 500 s 500 s

PG_B1

PG_B2

PG_B3

PG_B4

5 ms

5.7V

50 ms

LP8728B-Q1

www.ti.com

SNVSA70 – FEBRUARY 2015

Feature Description (continued)

If an overvoltage condition has lasted more than 50 ms, the power-good signals are released high once the

corresponding output voltage has settled. Regulators are started in a buck1

→ buck2 → buck3 → buck4

sequence. A 500-µs delay is included between each buck start-up (Figure 13). If an overvoltage condition has

lasted less than 5 ms, the buck converters are not shut down. Even in this case the PG_Bx pins are held low for

50 ms.

NOTE

Since the regulators are allowed to operate for 5 ms during overvoltage condition it is the

system designer’s responsibility to verify that input voltage doesn’t exceed limits stated in

Absolute Maximum Ratings. Exceeding these limits may cause permanent damage to the

device.

Figure 13. OVP Duration More Than 50 ms

7.4 Device Functional Modes

7.4.1 Shutdown Mode

When all EN_Bx inputs are low, the device is in a Shutdown mode. This is a low-power mode when all buck-

regulators and all internal blocks are disabled.

7.4.2 Active Mode

When the first enable pin is pulled high there is a 420-µs start-up delay when the device wakes up from the

Shutdown; mode and all internal reference blocks are started up. Once the reference blocks have settled, the

corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during

start-up. Once a buck output reaches 96% (typical) of the desired output voltage, the power-good pin is pulled

high. When at least one buck converter is active device is in a Active mode. When device is in Active mode, the

remaining buck converters will start up without any start-up delay when EN_Bx pin is pulled high. When EN_Bx

pin is set low the corresponding buck converter will shut down. When all EN_Bx pins are set low the device shuts

down all internal reference blocks and enters Shutdown mode.

If output voltage of a buck regulator falls below 93% (typical) of desired voltage due to, for example, an overload

condition, the corresponding power good pin is pulled low. Once the output voltage rises back above 96%

(typical) of desired voltage power good pin is set back high. Power good signal is held low for at least 50 ms.

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