VOUT1

VOUT2

VOUT3

VOUT4

Junction

Temperature TJ

TSD

(Internal Signal)

2s

500us 500us 500us

PG_B1

PG_B2

PG_B3

PG_B4

5 ms

130°C

150°C

96%

VOUTx

EN_Bx

PG_Bx

93%

Overload condition

5%

TSTART

TRAMP

50ms

Active pulldown

LP8728B-Q1

www.ti.com

SNVSA70 – FEBRUARY 2015

7.3 Feature Description

7.3.1 Buck Information

The buck converters are operated in a forced PWM mode. Even with light load a minimum switching pulse is

generated with every switching cycle. Each buck converter's high-side switch turn-on time is phase shifted to

minimize the input current ripple (see Figure 20).

7.3.1.1 Features

The following features are supported for all converters:

•

Synchronous rectification

•

Current mode feedback loop with PI compensator

•

Forced PWM operation

•

Soft start

•

Power-good output

•

Overvoltage comparator

In addition to the aforementioned features, Buck3 output voltage can be selected with the DEFSEL pin. If the

DEFSEL pin is pulled low, VOUT3 is set to 1.8 V. If DEFSEL is pulled high, VOUT3 is set to 2.65 V.

Figure 9. Buck Converter Start-up And Shutdown

7.3.2 Thermal Shutdown (TSD)

Thermal shutdown function shuts down all buck regulators if the device's junction temperature TJ rises above

150°C (typ.). All power-good signals are pulled low 5 ms before the buck regulators are shut down. Once TJ falls

below 130°C (typical), the LP8728 will automatically start up the buck regulators. There is a 2-second safety

delay included in the restart function. Buck regulators are not restarted until 2 seconds have elapsed after TJ falls

below 130°C (typical). To minimize the inrush current during restarting, regulators are started in a Buck1

→

Buck2

→ Buck3 → Buck4 sequence. A 500-µs delay is included between each buck start-up.

Figure 10. TSD Timing Diagram

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