VOUT1

VOUT2

VOUT3

VOUT4

VIN

OVP

PG_B1

PG_B2

PG_B3

PG_B4

5 ms

5.7V

50 ms

500 s 500 s 500 s

VIN

UVLO

PG_B1

PG_B2

PG_B3

PG_B4

VOUT1

VOUT3

VOUT4

VOUT2

2.7V

3.3V

5.0V

LP8728B-Q1

SNVSA70 – FEBRUARY 2015

www.ti.com

Feature Description (continued)

7.3.3 Undervoltage Lockout (UVLO)

If input voltage drops below 2.7 V (typ.) the PG_Bx pins are pulled low and the buck converters are shut down.

(Figure 11). The PG_Bx pins are always held low for at least 50 ms. The buck converters are restarted once the

input voltage rises above UVLO level.

If a UVLO condition has lasted less than 50 ms, the PG_Bx pins are released high once 50 ms has elapsed and

corresponding output voltage has settled. If an overvoltage condition has lasted more than 50 ms, the PG_Bx

pins are released high once corresponding output voltage has settled.

Regulators are always restarted in a Buck1

→ Buck2 → Buck3 → Buck4 sequence. A 500-µs delay is included

between each buck start-up.

Figure 11. UVLO Operation

7.3.4 Overvoltage Protection (OVP)

Overvoltage protection protects the device in case of an overvoltage condition. If input voltage exceeds 5.7 V

(typical), all PG_Bx pins are pulled low. the PG_Bx pins are always held low for at least 50 ms. Once the PG_Bx

pins are pulled low, the system has 5 ms time to power down. After an overvoltage condition has lasted for 5 ms,

all buck converters are shut down. The buck converters are restarted once input voltage falls below 5.62 V

(typical). The buck converters are started in a Buck1

→ Buck2 → Buck3 → Buck4 sequence. A 500-µs delay is

included between each buck start-up.

If an overvoltage condition lasted more than 5 ms, but less than 50 ms, the PG_Bx pins are released high once

50 ms has elapsed and the corresponding output voltage has settled (Figure 12).

Figure 12. OVP Duration Less Than 50 ms

12

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